Loading arch/xtensa/Kconfig +1 −0 Original line number Diff line number Diff line Loading @@ -16,6 +16,7 @@ config XTENSA select ARCH_WANT_OPTIONAL_GPIOLIB select CLONE_BACKWARDS select IRQ_DOMAIN select GENERIC_SIGALTSTACK help Xtensa processors are 32-bit RISC machines designed by Tensilica primarily for embedded systems. These processors are both Loading arch/xtensa/include/asm/syscall.h +0 −1 Original line number Diff line number Diff line Loading @@ -12,7 +12,6 @@ struct pt_regs; asmlinkage long xtensa_ptrace(long, long, long, long); asmlinkage long xtensa_sigreturn(struct pt_regs*); asmlinkage long xtensa_rt_sigreturn(struct pt_regs*); asmlinkage long xtensa_sigaltstack(struct pt_regs *regs); asmlinkage long xtensa_shmat(int, char __user *, int); asmlinkage long xtensa_fadvise64_64(int, int, unsigned long long, unsigned long long); Loading arch/xtensa/include/uapi/asm/unistd.h +1 −1 Original line number Diff line number Diff line Loading @@ -483,7 +483,7 @@ __SYSCALL(222, sys_ni_syscall, 0) #define __NR_restart_syscall 223 __SYSCALL(223, sys_restart_syscall, 0) #define __NR_sigaltstack 224 __SYSCALL(224, xtensa_sigaltstack, 2) __SYSCALL(224, sys_sigaltstack, 2) #define __NR_rt_sigreturn 225 __SYSCALL(225, xtensa_rt_sigreturn, 1) #define __NR_rt_sigaction 226 Loading arch/xtensa/kernel/signal.c +2 −16 Original line number Diff line number Diff line Loading @@ -265,7 +265,7 @@ asmlinkage long xtensa_rt_sigreturn(long a0, long a1, long a2, long a3, ret = regs->areg[2]; if (do_sigaltstack(&frame->uc.uc_stack, NULL, regs->areg[1]) == -EFAULT) if (restore_altstack(&frame->uc.uc_stack)) goto badframe; return ret; Loading Loading @@ -368,11 +368,7 @@ static int setup_frame(int sig, struct k_sigaction *ka, siginfo_t *info, err |= __put_user(0, &frame->uc.uc_flags); err |= __put_user(0, &frame->uc.uc_link); err |= __put_user((void *)current->sas_ss_sp, &frame->uc.uc_stack.ss_sp); err |= __put_user(sas_ss_flags(regs->areg[1]), &frame->uc.uc_stack.ss_flags); err |= __put_user(current->sas_ss_size, &frame->uc.uc_stack.ss_size); err |= __save_altstack(&frame->uc.uc_stack, regs->areg[1]); err |= setup_sigcontext(frame, regs); err |= __copy_to_user(&frame->uc.uc_sigmask, set, sizeof(*set)); Loading Loading @@ -424,16 +420,6 @@ give_sigsegv: return -EFAULT; } asmlinkage long xtensa_sigaltstack(const stack_t __user *uss, stack_t __user *uoss, long a2, long a3, long a4, long a5, struct pt_regs *regs) { return do_sigaltstack(uss, uoss, regs->areg[1]); } /* * Note that 'init' is a special process: it doesn't get signals it doesn't * want to handle. Thus you cannot kill init even with a SIGKILL even by Loading Loading
arch/xtensa/Kconfig +1 −0 Original line number Diff line number Diff line Loading @@ -16,6 +16,7 @@ config XTENSA select ARCH_WANT_OPTIONAL_GPIOLIB select CLONE_BACKWARDS select IRQ_DOMAIN select GENERIC_SIGALTSTACK help Xtensa processors are 32-bit RISC machines designed by Tensilica primarily for embedded systems. These processors are both Loading
arch/xtensa/include/asm/syscall.h +0 −1 Original line number Diff line number Diff line Loading @@ -12,7 +12,6 @@ struct pt_regs; asmlinkage long xtensa_ptrace(long, long, long, long); asmlinkage long xtensa_sigreturn(struct pt_regs*); asmlinkage long xtensa_rt_sigreturn(struct pt_regs*); asmlinkage long xtensa_sigaltstack(struct pt_regs *regs); asmlinkage long xtensa_shmat(int, char __user *, int); asmlinkage long xtensa_fadvise64_64(int, int, unsigned long long, unsigned long long); Loading
arch/xtensa/include/uapi/asm/unistd.h +1 −1 Original line number Diff line number Diff line Loading @@ -483,7 +483,7 @@ __SYSCALL(222, sys_ni_syscall, 0) #define __NR_restart_syscall 223 __SYSCALL(223, sys_restart_syscall, 0) #define __NR_sigaltstack 224 __SYSCALL(224, xtensa_sigaltstack, 2) __SYSCALL(224, sys_sigaltstack, 2) #define __NR_rt_sigreturn 225 __SYSCALL(225, xtensa_rt_sigreturn, 1) #define __NR_rt_sigaction 226 Loading
arch/xtensa/kernel/signal.c +2 −16 Original line number Diff line number Diff line Loading @@ -265,7 +265,7 @@ asmlinkage long xtensa_rt_sigreturn(long a0, long a1, long a2, long a3, ret = regs->areg[2]; if (do_sigaltstack(&frame->uc.uc_stack, NULL, regs->areg[1]) == -EFAULT) if (restore_altstack(&frame->uc.uc_stack)) goto badframe; return ret; Loading Loading @@ -368,11 +368,7 @@ static int setup_frame(int sig, struct k_sigaction *ka, siginfo_t *info, err |= __put_user(0, &frame->uc.uc_flags); err |= __put_user(0, &frame->uc.uc_link); err |= __put_user((void *)current->sas_ss_sp, &frame->uc.uc_stack.ss_sp); err |= __put_user(sas_ss_flags(regs->areg[1]), &frame->uc.uc_stack.ss_flags); err |= __put_user(current->sas_ss_size, &frame->uc.uc_stack.ss_size); err |= __save_altstack(&frame->uc.uc_stack, regs->areg[1]); err |= setup_sigcontext(frame, regs); err |= __copy_to_user(&frame->uc.uc_sigmask, set, sizeof(*set)); Loading Loading @@ -424,16 +420,6 @@ give_sigsegv: return -EFAULT; } asmlinkage long xtensa_sigaltstack(const stack_t __user *uss, stack_t __user *uoss, long a2, long a3, long a4, long a5, struct pt_regs *regs) { return do_sigaltstack(uss, uoss, regs->areg[1]); } /* * Note that 'init' is a special process: it doesn't get signals it doesn't * want to handle. Thus you cannot kill init even with a SIGKILL even by Loading