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Commit 03752f5b authored by Ben Widawsky's avatar Ben Widawsky Committed by Daniel Vetter
Browse files

drm/i915: Calculate correct stolen size for GEN7+ 



This bug existed in the old code, but was easier to fix here in the
rework. Unfortunately gen7 doesn't have a nice way to figure out the
size and we must use a lookup table.

As Jesse pointed out, there is some confusion in the docs about these
definitions. We're picking the one which seems more accurate, but we
really aren't certain.

Signed-off-by: default avatarBen Widawsky <ben@bwidawsk.net>
Reviewed-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent e76e9aeb

drivers/gpu/drm/i915/i915_gem_gtt.c

+13 −1
Original line number Diff line number Diff line
@@ -512,6 +512,15 @@ static inline unsigned int gen6_get_stolen_size(u16 snb_gmch_ctl) 
	return snb_gmch_ctl << 25; /* 32 MB units */

}



static inline unsigned int gen7_get_stolen_size(u16 snb_gmch_ctl)

{

	static const int stolen_decoder[] = {

		0, 0, 0, 0, 0, 32, 48, 64, 128, 256, 96, 160, 224, 352};

	snb_gmch_ctl >>= IVB_GMCH_GMS_SHIFT;

	snb_gmch_ctl &= IVB_GMCH_GMS_MASK;

	return stolen_decoder[snb_gmch_ctl] << 20;

}



int i915_gem_gtt_init(struct drm_device *dev)

{

	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -557,7 +566,10 @@ int i915_gem_gtt_init(struct drm_device *dev) 
	pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);

	dev_priv->mm.gtt->gtt_total_entries =

		gen6_get_total_gtt_size(snb_gmch_ctl) / sizeof(gtt_pte_t);

	if (INTEL_INFO(dev)->gen < 7)

		dev_priv->mm.gtt->stolen_size = gen6_get_stolen_size(snb_gmch_ctl);

	else

		dev_priv->mm.gtt->stolen_size = gen7_get_stolen_size(snb_gmch_ctl);



	dev_priv->mm.gtt->gtt_mappable_entries = pci_resource_len(dev->pdev, 2) >> PAGE_SHIFT;

	/* 64/512MB is the current min/max we actually know of, but this is just a

drivers/gpu/drm/i915/i915_reg.h

+2 −0
Original line number Diff line number Diff line
@@ -46,6 +46,8 @@ 
#define    SNB_GMCH_GGMS_MASK	0x3

#define    SNB_GMCH_GMS_SHIFT   3 /* Graphics Mode Select */

#define    SNB_GMCH_GMS_MASK    0x1f

#define    IVB_GMCH_GMS_SHIFT   4

#define    IVB_GMCH_GMS_MASK    0xf





/* PCI config space */