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Commit 03195c6b authored by Andi Kleen's avatar Andi Kleen Committed by H. Peter Anvin
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x86, mce, cmci: define MSR names and fields for new CMCI registers 



Impact: New register definitions only

CMCI means support for raising an interrupt on a corrected machine
check event instead of having to poll for it. It's a new feature in
Intel Nehalem CPUs available on some machine check banks.

For details see the IA32 SDM Vol3a 14.5

Define the registers for it as a preparation for further patches.

Signed-off-by: default avatarAndi Kleen <ak@linux.intel.com>
Signed-off-by: default avatarH. Peter Anvin <hpa@zytor.com>
parent ee031c31

arch/x86/include/asm/apicdef.h

+1 −0
Original line number Diff line number Diff line
@@ -53,6 +53,7 @@ 
#define		APIC_ESR_SENDILL	0x00020

#define		APIC_ESR_RECVILL	0x00040

#define		APIC_ESR_ILLREGA	0x00080

#define 	APIC_LVTCMCI	0x2f0

#define	APIC_ICR	0x300

#define		APIC_DEST_SELF		0x40000

#define		APIC_DEST_ALLINC	0x80000

arch/x86/include/asm/mce.h

+2 −0
Original line number Diff line number Diff line
@@ -11,6 +11,8 @@ 
 */



#define MCG_CTL_P	 (1UL<<8)   /* MCG_CAP register available */

#define MCG_EXT_P	 (1ULL<<9)   /* Extended registers available */

#define MCG_CMCI_P	 (1ULL<<10)  /* CMCI supported */



#define MCG_STATUS_RIPV  (1UL<<0)   /* restart ip valid */

#define MCG_STATUS_EIPV  (1UL<<1)   /* ip points to correct instruction */

arch/x86/include/asm/msr-index.h

+5 −0
Original line number Diff line number Diff line
@@ -77,6 +77,11 @@ 
#define MSR_IA32_MC0_ADDR		0x00000402

#define MSR_IA32_MC0_MISC		0x00000403



/* These are consecutive and not in the normal 4er MCE bank block */

#define MSR_IA32_MC0_CTL2		0x00000280

#define CMCI_EN			(1ULL << 30)

#define CMCI_THRESHOLD_MASK		0xffffULL



#define MSR_P6_PERFCTR0			0x000000c1

#define MSR_P6_PERFCTR1			0x000000c2

#define MSR_P6_EVNTSEL0			0x00000186