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Commit 02ac5b3f authored by Jason Cooper's avatar Jason Cooper
Browse files

Merge tag 'tags/cleanup_for_v3.10' into mvebu/soc 

mvebu cleanup for v3.10

 - plat-orion: prep for mvebu-mbus driver
parents 8d007488 3e762c86

arch/arm/mach-orion5x/pci.c

+4 −3
Original line number Diff line number Diff line
@@ -402,8 +402,9 @@ static void __init orion5x_pci_master_slave_enable(void) 
	orion5x_pci_hw_wr_conf(bus_nr, 0, func, reg, 4, val | 0x7);

}



static void __init orion5x_setup_pci_wins(struct mbus_dram_target_info *dram)

static void __init orion5x_setup_pci_wins(void)

{

	const struct mbus_dram_target_info *dram = mv_mbus_dram_info();

	u32 win_enable;

	int bus;

	int i;
@@ -420,7 +421,7 @@ static void __init orion5x_setup_pci_wins(struct mbus_dram_target_info *dram) 
	bus = orion5x_pci_local_bus_nr();



	for (i = 0; i < dram->num_cs; i++) {

		struct mbus_dram_window *cs = dram->cs + i;

		const struct mbus_dram_window *cs = dram->cs + i;

		u32 func = PCI_CONF_FUNC_BAR_CS(cs->cs_index);

		u32 reg;

		u32 val;
@@ -467,7 +468,7 @@ static int __init pci_setup(struct pci_sys_data *sys) 
	/*

	 * Point PCI unit MBUS decode windows to DRAM space.

	 */

	orion5x_setup_pci_wins(&orion_mbus_dram_info);

	orion5x_setup_pci_wins();



	/*

	 * Master + Slave enable

arch/arm/plat-orion/Makefile

+5 −1
Original line number Diff line number Diff line
@@ -3,7 +3,11 @@ 
#

ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include



obj-y                             += addr-map.o

obj-$(CONFIG_ARCH_MVEBU)          += addr-map.o

obj-$(CONFIG_ARCH_KIRKWOOD)       += addr-map.o

obj-$(CONFIG_ARCH_DOVE)           += addr-map.o

obj-$(CONFIG_ARCH_ORION5X)        += addr-map.o

obj-$(CONFIG_ARCH_MV78XX0)        += addr-map.o



orion-gpio-$(CONFIG_GENERIC_GPIO) += gpio.o

obj-$(CONFIG_PLAT_ORION_LEGACY)   += irq.o pcie.o time.o common.o mpp.o

arch/arm/plat-orion/pcie.c

+6 −4
Original line number Diff line number Diff line
@@ -120,12 +120,14 @@ void __init orion_pcie_reset(void __iomem *base) 
 * BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks

 * WIN[0-3] -> DRAM bank[0-3]

 */

static void __init orion_pcie_setup_wins(void __iomem *base,

					 struct mbus_dram_target_info *dram)

static void __init orion_pcie_setup_wins(void __iomem *base)

{

	const struct mbus_dram_target_info *dram;

	u32 size;

	int i;



	dram = mv_mbus_dram_info();



	/*

	 * First, disable and clear BARs and windows.

	 */
@@ -150,7 +152,7 @@ static void __init orion_pcie_setup_wins(void __iomem *base, 
	 */

	size = 0;

	for (i = 0; i < dram->num_cs; i++) {

		struct mbus_dram_window *cs = dram->cs + i;

		const struct mbus_dram_window *cs = dram->cs + i;



		writel(cs->base & 0xffff0000, base + PCIE_WIN04_BASE_OFF(i));

		writel(0, base + PCIE_WIN04_REMAP_OFF(i));
@@ -184,7 +186,7 @@ void __init orion_pcie_setup(void __iomem *base) 
	/*

	 * Point PCIe unit MBUS decode windows to DRAM space.

	 */

	orion_pcie_setup_wins(base, &orion_mbus_dram_info);

	orion_pcie_setup_wins(base);



	/*

	 * Master + slave enable.