Loading arch/arm/boot/dts/qcom/msm8917-pm.dtsi +6 −0 Original line number Diff line number Diff line Loading @@ -33,6 +33,12 @@ qcom,use-psci; #address-cells = <1>; #size-cells = <0>; clock-names = "cpu0_clk", "cpu1_clk", "cpu2_clk", "cpu3_clk"; clocks = <&clock_cpu clk_a53_bc_clk>, <&clock_cpu clk_a53_bc_clk>, <&clock_cpu clk_a53_bc_clk>, <&clock_cpu clk_a53_bc_clk>; qcom,pm-cluster@0{ reg = <0>; Loading arch/arm/boot/dts/qcom/msm8937-pm.dtsi +12 −0 Original line number Diff line number Diff line Loading @@ -36,6 +36,18 @@ qcom,use-psci; #address-cells = <1>; #size-cells = <0>; clock-names = "l2_clk", "cpu0_clk", "cpu1_clk", "cpu2_clk", "cpu3_clk", "cpu4_clk", "cpu5_clk", "cpu6_clk", "cpu7_clk"; clocks = <&clock_cpu clk_cci_clk>, <&clock_cpu clk_a53_bc_clk>, <&clock_cpu clk_a53_bc_clk>, <&clock_cpu clk_a53_bc_clk>, <&clock_cpu clk_a53_bc_clk>, <&clock_cpu clk_a53_lc_clk>, <&clock_cpu clk_a53_lc_clk>, <&clock_cpu clk_a53_lc_clk>, <&clock_cpu clk_a53_lc_clk>; qcom,pm-cluster@0 { reg = <0>; Loading arch/arm/boot/dts/qcom/msm8953-pm.dtsi +12 −0 Original line number Diff line number Diff line Loading @@ -38,6 +38,18 @@ qcom,use-psci; #address-cells = <1>; #size-cells = <0>; clock-names = "l2_clk", "cpu0_clk", "cpu1_clk", "cpu2_clk", "cpu3_clk", "cpu4_clk", "cpu5_clk", "cpu6_clk", "cpu7_clk"; clocks = <&clock_cpu clk_cci_clk>, <&clock_cpu clk_a53_pwr_clk>, <&clock_cpu clk_a53_pwr_clk>, <&clock_cpu clk_a53_pwr_clk>, <&clock_cpu clk_a53_pwr_clk>, <&clock_cpu clk_a53_pwr_clk>, <&clock_cpu clk_a53_pwr_clk>, <&clock_cpu clk_a53_pwr_clk>, <&clock_cpu clk_a53_pwr_clk>; qcom,pm-cluster@0 { reg = <0>; Loading Loading
arch/arm/boot/dts/qcom/msm8917-pm.dtsi +6 −0 Original line number Diff line number Diff line Loading @@ -33,6 +33,12 @@ qcom,use-psci; #address-cells = <1>; #size-cells = <0>; clock-names = "cpu0_clk", "cpu1_clk", "cpu2_clk", "cpu3_clk"; clocks = <&clock_cpu clk_a53_bc_clk>, <&clock_cpu clk_a53_bc_clk>, <&clock_cpu clk_a53_bc_clk>, <&clock_cpu clk_a53_bc_clk>; qcom,pm-cluster@0{ reg = <0>; Loading
arch/arm/boot/dts/qcom/msm8937-pm.dtsi +12 −0 Original line number Diff line number Diff line Loading @@ -36,6 +36,18 @@ qcom,use-psci; #address-cells = <1>; #size-cells = <0>; clock-names = "l2_clk", "cpu0_clk", "cpu1_clk", "cpu2_clk", "cpu3_clk", "cpu4_clk", "cpu5_clk", "cpu6_clk", "cpu7_clk"; clocks = <&clock_cpu clk_cci_clk>, <&clock_cpu clk_a53_bc_clk>, <&clock_cpu clk_a53_bc_clk>, <&clock_cpu clk_a53_bc_clk>, <&clock_cpu clk_a53_bc_clk>, <&clock_cpu clk_a53_lc_clk>, <&clock_cpu clk_a53_lc_clk>, <&clock_cpu clk_a53_lc_clk>, <&clock_cpu clk_a53_lc_clk>; qcom,pm-cluster@0 { reg = <0>; Loading
arch/arm/boot/dts/qcom/msm8953-pm.dtsi +12 −0 Original line number Diff line number Diff line Loading @@ -38,6 +38,18 @@ qcom,use-psci; #address-cells = <1>; #size-cells = <0>; clock-names = "l2_clk", "cpu0_clk", "cpu1_clk", "cpu2_clk", "cpu3_clk", "cpu4_clk", "cpu5_clk", "cpu6_clk", "cpu7_clk"; clocks = <&clock_cpu clk_cci_clk>, <&clock_cpu clk_a53_pwr_clk>, <&clock_cpu clk_a53_pwr_clk>, <&clock_cpu clk_a53_pwr_clk>, <&clock_cpu clk_a53_pwr_clk>, <&clock_cpu clk_a53_pwr_clk>, <&clock_cpu clk_a53_pwr_clk>, <&clock_cpu clk_a53_pwr_clk>, <&clock_cpu clk_a53_pwr_clk>; qcom,pm-cluster@0 { reg = <0>; Loading