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Commit 020ff546 authored by Marek Olšák's avatar Marek Olšák Committed by Christian König
Browse files

drm/radeon: set PIPE_CONFIG for 1D and linear tiling modes on CIK 



This fixes fast color clear with 1D-tiled single-sample surfaces
and Hyper-Z corruption with 1D-tiled depth surfaces.

Even though it seems it is not needed for 1D tiling, CMASK and HTILE are
always 2D-tiled, thus the hw needs to know the actual pipe configuration
for CMASK and HTILE addressing no matter what the tiling mode of the surface
is.

Signed-off-by: default avatarMarek Olšák <marek.olsak@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarChristian König <christian.koenig@amd.com>
parent ab8f1a2a

drivers/gpu/drm/radeon/cik.c

+24 −3
Original line number Original line Diff line number Diff line
@@ -2029,6 +2029,7 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev) 
				break;

				break;

			case 5:

			case 5:

				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |

				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |

						 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |

						 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));

						 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));

				break;

				break;

			case 6:

			case 6:
@@ -2049,6 +2050,7 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev) 
				break;

				break;

			case 9:

			case 9:

				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |

				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |

						 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |

						 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));

						 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));

				break;

				break;

			case 10:

			case 10:
@@ -2071,6 +2073,7 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev) 
				break;

				break;

			case 13:

			case 13:

				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |

				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |

						 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |

						 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));

						 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));

				break;

				break;

			case 14:

			case 14:
@@ -2093,6 +2096,7 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev) 
				break;

				break;

			case 27:

			case 27:

				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |

				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |

						 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |

						 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));

						 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));

				break;

				break;

			case 28:

			case 28:
@@ -2247,6 +2251,7 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev) 
				break;

				break;

			case 5:

			case 5:

				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |

				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |

						 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |

						 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));

						 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));

				break;

				break;

			case 6:

			case 6:
@@ -2267,6 +2272,7 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev) 
				break;

				break;

			case 9:

			case 9:

				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |

				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |

						 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |

						 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));

						 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));

				break;

				break;

			case 10:

			case 10:
@@ -2289,6 +2295,7 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev) 
				break;

				break;

			case 13:

			case 13:

				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |

				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |

						 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |

						 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));

						 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));

				break;

				break;

			case 14:

			case 14:
@@ -2311,6 +2318,7 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev) 
				break;

				break;

			case 27:

			case 27:

				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |

				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |

						 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |

						 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));

						 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));

				break;

				break;

			case 28:

			case 28:
@@ -2467,6 +2475,7 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev) 
					break;

					break;

				case 5:

				case 5:

					gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |

					gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |

							 PIPE_CONFIG(ADDR_SURF_P4_16x16) |

							 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));

							 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));

					break;

					break;

				case 6:

				case 6:
@@ -2487,6 +2496,7 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev) 
					break;

					break;

				case 9:

				case 9:

					gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |

					gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |

							 PIPE_CONFIG(ADDR_SURF_P4_16x16) |

							 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));

							 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));

					break;

					break;

				case 10:

				case 10:
@@ -2509,6 +2519,7 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev) 
					break;

					break;

				case 13:

				case 13:

					gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |

					gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |

							 PIPE_CONFIG(ADDR_SURF_P4_16x16) |

							 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));

							 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));

					break;

					break;

				case 14:

				case 14:
@@ -2531,6 +2542,7 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev) 
					break;

					break;

				case 27:

				case 27:

					gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |

					gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |

							 PIPE_CONFIG(ADDR_SURF_P4_16x16) |

							 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));

							 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));

					break;

					break;

				case 28:

				case 28:
@@ -2593,6 +2605,7 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev) 
					break;

					break;

				case 5:

				case 5:

					gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |

					gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |

							 PIPE_CONFIG(ADDR_SURF_P4_8x16) |

							 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));

							 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));

					break;

					break;

				case 6:

				case 6:
@@ -2613,6 +2626,7 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev) 
					break;

					break;

				case 9:

				case 9:

					gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |

					gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |

							 PIPE_CONFIG(ADDR_SURF_P4_8x16) |

							 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));

							 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));

					break;

					break;

				case 10:

				case 10:
@@ -2635,6 +2649,7 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev) 
					break;

					break;

				case 13:

				case 13:

					gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |

					gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |

							 PIPE_CONFIG(ADDR_SURF_P4_8x16) |

							 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));

							 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));

					break;

					break;

				case 14:

				case 14:
@@ -2657,6 +2672,7 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev) 
					break;

					break;

				case 27:

				case 27:

					gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |

					gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |

							 PIPE_CONFIG(ADDR_SURF_P4_8x16) |

							 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));

							 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));

					break;

					break;

				case 28:

				case 28:
@@ -2813,6 +2829,7 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev) 
				break;

				break;

			case 5:

			case 5:

				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |

				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |

						 PIPE_CONFIG(ADDR_SURF_P2) |

						 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));

						 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));

				break;

				break;

			case 6:

			case 6:
@@ -2828,11 +2845,13 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev) 
						 TILE_SPLIT(split_equal_to_row_size));

						 TILE_SPLIT(split_equal_to_row_size));

				break;

				break;

			case 8:

			case 8:

				gb_tile_moden = ARRAY_MODE(ARRAY_LINEAR_ALIGNED);

				gb_tile_moden = ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |

						PIPE_CONFIG(ADDR_SURF_P2);

				break;

				break;

			case 9:

			case 9:

				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |

				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |

						 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));

						 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |

						 PIPE_CONFIG(ADDR_SURF_P2));

				break;

				break;

			case 10:

			case 10:

				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
@@ -2854,6 +2873,7 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev) 
				break;

				break;

			case 13:

			case 13:

				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |

				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |

						 PIPE_CONFIG(ADDR_SURF_P2) |

						 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));

						 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));

				break;

				break;

			case 14:

			case 14:
@@ -2876,7 +2896,8 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev) 
				break;

				break;

			case 27:

			case 27:

				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |

				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |

						 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));

						 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |

						 PIPE_CONFIG(ADDR_SURF_P2));

				break;

				break;

			case 28:

			case 28:

				gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |

				gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |

drivers/gpu/drm/radeon/radeon_drv.c

+2 −1
Original line number Original line Diff line number Diff line
@@ -79,7 +79,8 @@ 
 *   2.35.0 - Add CIK macrotile mode array query

 *   2.35.0 - Add CIK macrotile mode array query

 *   2.36.0 - Fix CIK DCE tiling setup

 *   2.36.0 - Fix CIK DCE tiling setup

 *   2.37.0 - allow GS ring setup on r6xx/r7xx

 *   2.37.0 - allow GS ring setup on r6xx/r7xx

 *   2.38.0 - RADEON_GEM_OP (GET_INITIAL_DOMAIN, SET_INITIAL_DOMAIN)

 *   2.38.0 - RADEON_GEM_OP (GET_INITIAL_DOMAIN, SET_INITIAL_DOMAIN),

 *            CIK: 1D and linear tiling modes contain valid PIPE_CONFIG

 */

 */

#define KMS_DRIVER_MAJOR	2

#define KMS_DRIVER_MAJOR	2

#define KMS_DRIVER_MINOR	38

#define KMS_DRIVER_MINOR	38