Commit 0173b3a7 authored Jul 09, 2015 by Mitchel Humpherys

iommu/io-pgtable-arm: Use non-cacheable page table memory



Requests from the walker to page table memory are currently inner- and
outer-cacheable.  This configuration hasn't been fully validated for
functionality or characterized for performance.  Configure these
requests as non-cacheable.

Change-Id: I7efb0a697faff68a67ee0afdb933b6dd6926f30a
Signed-off-by: Mitchel Humpherys <mitchelh@codeaurora.org>

parent c952020e

drivers/iommu/io-pgtable-arm.c

+2 −2

Original line number	Diff line number	Diff line
		@@ -680,8 +680,8 @@ arm_64_lpae_alloc_pgtable_s1(struct io_pgtable_cfg cfg, void cookie)

		/* TCR */
		reg = (ARM_LPAE_TCR_SH_IS << ARM_LPAE_TCR_SH0_SHIFT) \|
		(ARM_LPAE_TCR_RGN_WBWA << ARM_LPAE_TCR_IRGN0_SHIFT) \|
		(ARM_LPAE_TCR_RGN_WBWA << ARM_LPAE_TCR_ORGN0_SHIFT);
		(ARM_LPAE_TCR_RGN_NC << ARM_LPAE_TCR_IRGN0_SHIFT) \|
		(ARM_LPAE_TCR_RGN_NC << ARM_LPAE_TCR_ORGN0_SHIFT);

		switch (1 << data->pg_shift) {
		case SZ_4K: