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Commit 01628188 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'x86-cpu-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip 

* 'x86-cpu-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip:
  x86, cpu: Fix detection of Celeron Covington stepping A1 and B0
  Documentation, ABI: Update L3 cache index disable text
  x86, AMD, cacheinfo: Fix L3 cache index disable checks
  x86, AMD, cacheinfo: Fix fallout caused by max3 conversion
  x86, cpu: Change NOP selection for certain Intel CPUs
  x86, cpu: Clean up and unify the NOP selection infrastructure
  x86, percpu: Use ASM_NOP4 instead of hardcoding P6_NOP4
  x86, cpu: Move AMD Elan Kconfig under "Processor family"

Fix up trivial conflicts in alternative handling (commit dc326fca
"x86, cpu: Clean up and unify the NOP selection infrastructure" removed
some hacky 5-byte instruction stuff, while commit d430d3d7 "jump
label: Introduce static_branch() interface" renamed HAVE_JUMP_LABEL to
CONFIG_JUMP_LABEL in the code that went away)
parents 17b14180 865be7a8

Documentation/ABI/testing/sysfs-devices-system-cpu

+17 −17
Original line number Diff line number Diff line
@@ -183,21 +183,21 @@ Description: Discover and change clock speed of CPUs 
		to learn how to control the knobs.





What:      /sys/devices/system/cpu/cpu*/cache/index*/cache_disable_X

What:		/sys/devices/system/cpu/cpu*/cache/index3/cache_disable_{0,1}

Date:		August 2008

KernelVersion:	2.6.27

Contact:	mark.langsdorf@amd.com

Description:	These files exist in every cpu's cache index directories.

		There are currently 2 cache_disable_# files in each

		directory.  Reading from these files on a supported

		processor will return that cache disable index value

		for that processor and node.  Writing to one of these

		files will cause the specificed cache index to be disabled.



		Currently, only AMD Family 10h Processors support cache index

		disable, and only for their L3 caches.  See the BIOS and

		Kernel Developer's Guide at

		http://support.amd.com/us/Embedded_TechDocs/31116-Public-GH-BKDG_3-28_5-28-09.pdf	

		for formatting information and other details on the

		cache index disable.

Users:    joachim.deguara@amd.com
 
Contact:	discuss@x86-64.org

Description:	Disable L3 cache indices



		These files exist in every CPU's cache/index3 directory. Each

		cache_disable_{0,1} file corresponds to one disable slot which

		can be used to disable a cache index. Reading from these files

		on a processor with this functionality will return the currently

		disabled index for that node. There is one L3 structure per

		node, or per internal node on MCM machines. Writing a valid

		index to one of these files will cause the specificed cache

		index to be disabled.



		All AMD processors with L3 caches provide this functionality.

		For details, see BKDGs at

		http://developer.amd.com/documentation/guides/Pages/default.aspx

arch/x86/Kconfig

+0 −11
Original line number Diff line number Diff line
@@ -365,17 +365,6 @@ config X86_UV 
# Following is an alphabetically sorted list of 32 bit extended platforms

# Please maintain the alphabetic order if and when there are additions



config X86_ELAN

	bool "AMD Elan"

	depends on X86_32

	depends on X86_EXTENDED_PLATFORM

	---help---

	  Select this for an AMD Elan processor.



	  Do not use this option for K6/Athlon/Opteron processors!



	  If unsure, choose "PC-compatible" instead.



config X86_INTEL_CE

	bool "CE4100 TV platform"

	depends on PCI

arch/x86/Kconfig.cpu

+10 −6
Original line number Diff line number Diff line 
# Put here option for CPU selection and depending optimization

if !X86_ELAN



choice

	prompt "Processor family"

	default M686 if X86_32
@@ -203,6 +201,14 @@ config MWINCHIP3D 
	  stores for this CPU, which can increase performance of some

	  operations.



config MELAN

	bool "AMD Elan"

	depends on X86_32

	---help---

	  Select this for an AMD Elan processor.



	  Do not use this option for K6/Athlon/Opteron processors!



config MGEODEGX1

	bool "GeodeGX1"

	depends on X86_32
@@ -292,8 +298,6 @@ config X86_GENERIC 
	  This is really intended for distributors who need more

	  generic optimizations.



endif



#

# Define implied options from the CPU selection here

config X86_INTERNODE_CACHE_SHIFT
@@ -312,7 +316,7 @@ config X86_L1_CACHE_SHIFT 
	int

	default "7" if MPENTIUM4 || MPSC

	default "6" if MK7 || MK8 || MPENTIUMM || MCORE2 || MATOM || MVIAC7 || X86_GENERIC || GENERIC_CPU

	default "4" if X86_ELAN || M486 || M386 || MGEODEGX1

	default "4" if MELAN || M486 || M386 || MGEODEGX1

	default "5" if MWINCHIP3D || MWINCHIPC6 || MCRUSOE || MEFFICEON || MCYRIXIII || MK6 || MPENTIUMIII || MPENTIUMII || M686 || M586MMX || M586TSC || M586 || MVIAC3_2 || MGEODE_LX



config X86_XADD
@@ -358,7 +362,7 @@ config X86_POPAD_OK 


config X86_ALIGNMENT_16

	def_bool y

	depends on MWINCHIP3D || MWINCHIPC6 || MCYRIXIII || X86_ELAN || MK6 || M586MMX || M586TSC || M586 || M486 || MVIAC3_2 || MGEODEGX1

	depends on MWINCHIP3D || MWINCHIPC6 || MCYRIXIII || MELAN || MK6 || M586MMX || M586TSC || M586 || M486 || MVIAC3_2 || MGEODEGX1



config X86_INTEL_USERCOPY

	def_bool y

arch/x86/Makefile_32.cpu

+1 −1
Original line number Diff line number Diff line
@@ -37,7 +37,7 @@ cflags-$(CONFIG_MATOM) += $(call cc-option,-march=atom,$(call cc-option,-march= 
	$(call cc-option,-mtune=atom,$(call cc-option,-mtune=generic))



# AMD Elan support

cflags-$(CONFIG_X86_ELAN)	+= -march=i486

cflags-$(CONFIG_MELAN)		+= -march=i486



# Geode GX1 support

cflags-$(CONFIG_MGEODEGX1)	+= -march=pentium-mmx

arch/x86/include/asm/alternative.h

+0 −8
Original line number Diff line number Diff line
@@ -190,12 +190,4 @@ extern void *text_poke(void *addr, const void *opcode, size_t len); 
extern void *text_poke_smp(void *addr, const void *opcode, size_t len);

extern void text_poke_smp_batch(struct text_poke_param *params, int n);



#if defined(CONFIG_DYNAMIC_FTRACE) || defined(CONFIG_JUMP_LABEL)

#define IDEAL_NOP_SIZE_5 5

extern unsigned char ideal_nop5[IDEAL_NOP_SIZE_5];

extern void arch_init_ideal_nop5(void);

#else

static inline void arch_init_ideal_nop5(void) {}

#endif



#endif /* _ASM_X86_ALTERNATIVE_H */