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Commit 0116e1ef authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/radeon: use new cg/pg flags for SI 



Allows us finer grained control over clock and
powergating on SI.

Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 64d8a728

drivers/gpu/drm/radeon/radeon_asic.c

+98 −0
Original line number Diff line number Diff line
@@ -2335,6 +2335,104 @@ int radeon_asic_init(struct radeon_device *rdev) 
			rdev->has_uvd = false;

		else

			rdev->has_uvd = true;

		switch (rdev->family) {

		case CHIP_TAHITI:

			rdev->cg_flags =

				RADEON_CG_SUPPORT_GFX_MGCG |

				RADEON_CG_SUPPORT_GFX_MGLS |

				RADEON_CG_SUPPORT_GFX_CGCG |

				RADEON_CG_SUPPORT_GFX_CGLS |

				RADEON_CG_SUPPORT_GFX_CGTS |

				RADEON_CG_SUPPORT_GFX_CP_LS |

				RADEON_CG_SUPPORT_MC_MGCG |

				RADEON_CG_SUPPORT_SDMA_MGCG |

				RADEON_CG_SUPPORT_BIF_LS |

				RADEON_CG_SUPPORT_VCE_MGCG |

				RADEON_CG_SUPPORT_UVD_MGCG |

				RADEON_CG_SUPPORT_HDP_LS |

				RADEON_CG_SUPPORT_HDP_MGCG;

			rdev->pg_flags = 0;

			break;

		case CHIP_PITCAIRN:

			rdev->cg_flags =

				RADEON_CG_SUPPORT_GFX_MGCG |

				RADEON_CG_SUPPORT_GFX_MGLS |

				RADEON_CG_SUPPORT_GFX_CGCG |

				RADEON_CG_SUPPORT_GFX_CGLS |

				RADEON_CG_SUPPORT_GFX_CGTS |

				RADEON_CG_SUPPORT_GFX_CP_LS |

				RADEON_CG_SUPPORT_GFX_RLC_LS |

				RADEON_CG_SUPPORT_MC_LS |

				RADEON_CG_SUPPORT_MC_MGCG |

				RADEON_CG_SUPPORT_SDMA_MGCG |

				RADEON_CG_SUPPORT_BIF_LS |

				RADEON_CG_SUPPORT_VCE_MGCG |

				RADEON_CG_SUPPORT_UVD_MGCG |

				RADEON_CG_SUPPORT_HDP_LS |

				RADEON_CG_SUPPORT_HDP_MGCG;

			rdev->pg_flags = 0;

			break;

		case CHIP_VERDE:

			rdev->cg_flags =

				RADEON_CG_SUPPORT_GFX_MGCG |

				RADEON_CG_SUPPORT_GFX_MGLS |

				RADEON_CG_SUPPORT_GFX_CGCG |

				RADEON_CG_SUPPORT_GFX_CGLS |

				RADEON_CG_SUPPORT_GFX_CGTS |

				RADEON_CG_SUPPORT_GFX_CP_LS |

				RADEON_CG_SUPPORT_GFX_RLC_LS |

				RADEON_CG_SUPPORT_MC_LS |

				RADEON_CG_SUPPORT_MC_MGCG |

				RADEON_CG_SUPPORT_SDMA_MGCG |

				RADEON_CG_SUPPORT_BIF_LS |

				RADEON_CG_SUPPORT_VCE_MGCG |

				RADEON_CG_SUPPORT_UVD_MGCG |

				RADEON_CG_SUPPORT_HDP_LS |

				RADEON_CG_SUPPORT_HDP_MGCG;

			rdev->pg_flags = 0;

					/*RADEON_PG_SUPPORT_GFX_CG |

			  		  RADEON_PG_SUPPORT_SDMA;*/

			break;

		case CHIP_OLAND:

			rdev->cg_flags =

				RADEON_CG_SUPPORT_GFX_MGCG |

				RADEON_CG_SUPPORT_GFX_MGLS |

				RADEON_CG_SUPPORT_GFX_CGCG |

				RADEON_CG_SUPPORT_GFX_CGLS |

				RADEON_CG_SUPPORT_GFX_CGTS |

				RADEON_CG_SUPPORT_GFX_CP_LS |

				RADEON_CG_SUPPORT_GFX_RLC_LS |

				RADEON_CG_SUPPORT_MC_LS |

				RADEON_CG_SUPPORT_MC_MGCG |

				RADEON_CG_SUPPORT_SDMA_MGCG |

				RADEON_CG_SUPPORT_BIF_LS |

				RADEON_CG_SUPPORT_UVD_MGCG |

				RADEON_CG_SUPPORT_HDP_LS |

				RADEON_CG_SUPPORT_HDP_MGCG;

			rdev->pg_flags = 0;

			break;

		case CHIP_HAINAN:

			rdev->cg_flags =

				RADEON_CG_SUPPORT_GFX_MGCG |

				RADEON_CG_SUPPORT_GFX_MGLS |

				RADEON_CG_SUPPORT_GFX_CGCG |

				RADEON_CG_SUPPORT_GFX_CGLS |

				RADEON_CG_SUPPORT_GFX_CGTS |

				RADEON_CG_SUPPORT_GFX_CP_LS |

				RADEON_CG_SUPPORT_GFX_RLC_LS |

				RADEON_CG_SUPPORT_MC_LS |

				RADEON_CG_SUPPORT_MC_MGCG |

				RADEON_CG_SUPPORT_SDMA_MGCG |

				RADEON_CG_SUPPORT_BIF_LS |

				RADEON_CG_SUPPORT_HDP_LS |

				RADEON_CG_SUPPORT_HDP_MGCG;

			rdev->pg_flags = 0;

			break;

		default:

			rdev->cg_flags = 0;

			rdev->pg_flags = 0;

			break;

		}

		break;

	case CHIP_BONAIRE:

		rdev->asic = &ci_asic;

drivers/gpu/drm/radeon/si.c

+30 −29
Original line number Diff line number Diff line
@@ -5121,12 +5121,15 @@ static void si_enable_mc_ls(struct radeon_device *rdev, 


static void si_init_cg(struct radeon_device *rdev)

{

	if (rdev->cg_flags & RADEON_CG_SUPPORT_GFX_MGCG)

		si_enable_mgcg(rdev, true);

	si_enable_cgcg(rdev, false);

	/* disable MC LS on Tahiti */

	if (rdev->family == CHIP_TAHITI)

	if (rdev->cg_flags & RADEON_CG_SUPPORT_GFX_CGCG)

		si_enable_cgcg(rdev, false/*true*/);

	/* Disable MC LS on tahiti */

	if (!(rdev->cg_flags & RADEON_CG_SUPPORT_MC_LS))

		si_enable_mc_ls(rdev, false);

	if (rdev->has_uvd) {

		if (rdev->cg_flags & RADEON_CG_SUPPORT_UVD_MGCG)

			si_enable_uvd_mgcg(rdev, true);

		si_init_uvd_internal_cg(rdev);

	}
@@ -5134,26 +5137,28 @@ static void si_init_cg(struct radeon_device *rdev) 


static void si_fini_cg(struct radeon_device *rdev)

{

	if (rdev->has_uvd)

	if (rdev->has_uvd) {

		if (rdev->cg_flags & RADEON_CG_SUPPORT_UVD_MGCG)

			si_enable_uvd_mgcg(rdev, false);

	}

	if (rdev->cg_flags & RADEON_CG_SUPPORT_GFX_CGCG)

		si_enable_cgcg(rdev, false);

	if (rdev->cg_flags & RADEON_CG_SUPPORT_GFX_MGCG)

		si_enable_mgcg(rdev, false);

}



static void si_init_pg(struct radeon_device *rdev)

{

	bool has_pg = false;

#if 0

	/* only cape verde supports PG */

	if (rdev->family == CHIP_VERDE)

		has_pg = true;

#endif

	if (has_pg) {

		si_init_ao_cu_mask(rdev);

	if (rdev->pg_flags) {

		if (rdev->pg_flags & RADEON_PG_SUPPORT_SDMA) {

			si_init_dma_pg(rdev);

			si_enable_dma_pg(rdev, true);

		}

		si_init_ao_cu_mask(rdev);

		if (rdev->pg_flags & RADEON_PG_SUPPORT_GFX_CG) {

			si_init_gfx_cgpg(rdev);

			si_enable_gfx_cgpg(rdev, true);

		}

	} else {

		WREG32(RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8);

		WREG32(RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8);
@@ -5162,14 +5167,10 @@ static void si_init_pg(struct radeon_device *rdev) 


static void si_fini_pg(struct radeon_device *rdev)

{

	bool has_pg = false;



	/* only cape verde supports PG */

	if (rdev->family == CHIP_VERDE)

		has_pg = true;



	if (has_pg) {

	if (rdev->pg_flags) {

		if (rdev->pg_flags & RADEON_PG_SUPPORT_SDMA)

			si_enable_dma_pg(rdev, false);

		if (rdev->pg_flags & RADEON_PG_SUPPORT_GFX_CG)

			si_enable_gfx_cgpg(rdev, false);

	}

}