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Commit 01142519 authored by Illia Smyrnov's avatar Illia Smyrnov Committed by Paul Walmsley
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ARM: OMAP4: hwmod: Fix SOFTRESET logic for OMAP4 



Commit 313a76ee (ARM: OMAP2+: hwmod: Fix SOFTRESET logic) introduced
softreset bit cleaning right after set one. It is caused L3 error for
OMAP4 ISS because ISS register write occurs when ISS reset process is in
progress. Avoid this situation by cleaning softreset bit later, when reset
process is successfully finished.

Signed-off-by: default avatarIllia Smyrnov <illia.smyrnov@globallogic.com>
Reviewed-by: default avatarGrygorii Strashko <grygorii.strashko@ti.com>
Acked-by: default avatarRoger Quadros <rogerq@ti.com>
Signed-off-by: default avatarPaul Walmsley <paul@pwsan.com>
parent c317d0f2

arch/arm/mach-omap2/omap_hwmod.c

+11 −9
Original line number Diff line number Diff line
@@ -1946,30 +1946,32 @@ static int _ocp_softreset(struct omap_hwmod *oh) 
	if (ret)

		goto dis_opt_clks;



	_write_sysconfig(v, oh);

	ret = _clear_softreset(oh, &v);

	if (ret)

		goto dis_opt_clks;



	_write_sysconfig(v, oh);



	if (oh->class->sysc->srst_udelay)

		udelay(oh->class->sysc->srst_udelay);



	c = _wait_softreset_complete(oh);

	if (c == MAX_MODULE_SOFTRESET_WAIT)

	if (c == MAX_MODULE_SOFTRESET_WAIT) {

		pr_warning("omap_hwmod: %s: softreset failed (waited %d usec)\n",

			   oh->name, MAX_MODULE_SOFTRESET_WAIT);

	else

		ret = -ETIMEDOUT;

		goto dis_opt_clks;

	} else {

		pr_debug("omap_hwmod: %s: softreset in %d usec\n", oh->name, c);

	}



	ret = _clear_softreset(oh, &v);

	if (ret)

		goto dis_opt_clks;



	_write_sysconfig(v, oh);



	/*

	 * XXX add _HWMOD_STATE_WEDGED for modules that don't come back from

	 * _wait_target_ready() or _reset()

	 */



	ret = (c == MAX_MODULE_SOFTRESET_WAIT) ? -ETIMEDOUT : 0;



dis_opt_clks:

	if (oh->flags & HWMOD_CONTROL_OPT_CLKS_IN_RESET)

		_disable_optional_clocks(oh);