Commit 00e38afb authored May 25, 2015 by Ashay Jaiswal Committed by Abhijeet Dharmapurikar Jun 15, 2015

power: qpnp-fg: optimise FG SRAM bulk read/write logic



In case of Interleave Memory Access(IMA) protocol, software
needs to wait and poll for IACS Ready bit to be set across
each read/write operation.

FG hardware updates IACS bit 20-30 usec after the read/write
operation. Add a delay of 30 usec before reading IACS bit to
make sure FG hardware gets time to update (this reduces number
of polling retries and overall read/write time).

Change-Id: I4866c82f30d9271fa8bead09d26ec7eaba6f1f2b
Signed-off-by: Ashay Jaiswal <ashayj@codeaurora.org>

parent e4ea89f5

drivers/power/qpnp-fg.c

+7 −1

Original line number	Diff line number	Diff line
		@@ -1050,6 +1050,12 @@ static int fg_check_iacs_ready(struct fg_chip *chip)
		int rc = 0, timeout = 250;
		u8 ima_opr_sts = 0;

		/*
		* Additional delay to make sure IACS ready bit is set after
		* Read/Write operation.
		*/

		usleep_range(30, 35);
		while (1) {
		rc = fg_read(chip, &ima_opr_sts,
		chip->mem_base + MEM_INTF_IMA_OPR_STS, 1);
		@@ -1059,7 +1065,7 @@ static int fg_check_iacs_ready(struct fg_chip *chip)
		if (!(--timeout) \|\| rc)
		break;
		/* delay for iacs_ready to be asserted */
		usleep_range(10000, 12000);
		usleep_range(5000, 7000);
		}
		}