power: qpnp-fg: optimise FG SRAM bulk read/write logic

In case of Interleave Memory Access(IMA) protocol, software
needs to wait and poll for IACS Ready bit to be set across
each read/write operation.

FG hardware updates IACS bit 20-30 usec after the read/write
operation. Add a delay of 30 usec before reading IACS bit to
make sure FG hardware gets time to update (this reduces number
of polling retries and overall read/write time).

Change-Id: I4866c82f30d9271fa8bead09d26ec7eaba6f1f2b
Signed-off-by: Ashay Jaiswal <ashayj@codeaurora.org>