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Commit 005a8078 authored by Matt Wagantall's avatar Matt Wagantall
Browse files

Merge tag 'v3.18.11' into msm-3.18 



Linux 3.18.11

Resolve straight-forward conflicts in dma-mapping.c to
make room for the upstream change 0ef78141 ("arm64:
Honor __GFP_ZERO in dma allocations")

Conflicts:
	arch/arm64/mm/dma-mapping.c

Change-Id: Ic45b54f434072ddb5ddc747390706eaa1efed5d3
Signed-off-by: default avatarMatt Wagantall <mattw@codeaurora.org>
parents 3fcd7323 f154a14e

Makefile

+1 −1
Original line number Diff line number Diff line 
VERSION = 3

PATCHLEVEL = 18

SUBLEVEL = 10

SUBLEVEL = 11

EXTRAVERSION =

NAME = Shuffling Zombie Juror

arch/arm/boot/dts/am33xx-clocks.dtsi

+3 −3
Original line number Diff line number Diff line
@@ -99,7 +99,7 @@ 
	ehrpwm0_tbclk: ehrpwm0_tbclk@44e10664 {

		#clock-cells = <0>;

		compatible = "ti,gate-clock";

		clocks = <&dpll_per_m2_ck>;

		clocks = <&l4ls_gclk>;

		ti,bit-shift = <0>;

		reg = <0x0664>;

	};
@@ -107,7 +107,7 @@ 
	ehrpwm1_tbclk: ehrpwm1_tbclk@44e10664 {

		#clock-cells = <0>;

		compatible = "ti,gate-clock";

		clocks = <&dpll_per_m2_ck>;

		clocks = <&l4ls_gclk>;

		ti,bit-shift = <1>;

		reg = <0x0664>;

	};
@@ -115,7 +115,7 @@ 
	ehrpwm2_tbclk: ehrpwm2_tbclk@44e10664 {

		#clock-cells = <0>;

		compatible = "ti,gate-clock";

		clocks = <&dpll_per_m2_ck>;

		clocks = <&l4ls_gclk>;

		ti,bit-shift = <2>;

		reg = <0x0664>;

	};

arch/arm/boot/dts/am43xx-clocks.dtsi

+6 −6
Original line number Diff line number Diff line
@@ -107,7 +107,7 @@ 
	ehrpwm0_tbclk: ehrpwm0_tbclk {

		#clock-cells = <0>;

		compatible = "ti,gate-clock";

		clocks = <&dpll_per_m2_ck>;

		clocks = <&l4ls_gclk>;

		ti,bit-shift = <0>;

		reg = <0x0664>;

	};
@@ -115,7 +115,7 @@ 
	ehrpwm1_tbclk: ehrpwm1_tbclk {

		#clock-cells = <0>;

		compatible = "ti,gate-clock";

		clocks = <&dpll_per_m2_ck>;

		clocks = <&l4ls_gclk>;

		ti,bit-shift = <1>;

		reg = <0x0664>;

	};
@@ -123,7 +123,7 @@ 
	ehrpwm2_tbclk: ehrpwm2_tbclk {

		#clock-cells = <0>;

		compatible = "ti,gate-clock";

		clocks = <&dpll_per_m2_ck>;

		clocks = <&l4ls_gclk>;

		ti,bit-shift = <2>;

		reg = <0x0664>;

	};
@@ -131,7 +131,7 @@ 
	ehrpwm3_tbclk: ehrpwm3_tbclk {

		#clock-cells = <0>;

		compatible = "ti,gate-clock";

		clocks = <&dpll_per_m2_ck>;

		clocks = <&l4ls_gclk>;

		ti,bit-shift = <4>;

		reg = <0x0664>;

	};
@@ -139,7 +139,7 @@ 
	ehrpwm4_tbclk: ehrpwm4_tbclk {

		#clock-cells = <0>;

		compatible = "ti,gate-clock";

		clocks = <&dpll_per_m2_ck>;

		clocks = <&l4ls_gclk>;

		ti,bit-shift = <5>;

		reg = <0x0664>;

	};
@@ -147,7 +147,7 @@ 
	ehrpwm5_tbclk: ehrpwm5_tbclk {

		#clock-cells = <0>;

		compatible = "ti,gate-clock";

		clocks = <&dpll_per_m2_ck>;

		clocks = <&l4ls_gclk>;

		ti,bit-shift = <6>;

		reg = <0x0664>;

	};

arch/arm/boot/dts/dra7xx-clocks.dtsi

+81 −9
Original line number Diff line number Diff line
@@ -243,10 +243,18 @@ 
		ti,invert-autoidle-bit;

	};



	dpll_core_byp_mux: dpll_core_byp_mux {

		#clock-cells = <0>;

		compatible = "ti,mux-clock";

		clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;

		ti,bit-shift = <23>;

		reg = <0x012c>;

	};



	dpll_core_ck: dpll_core_ck {

		#clock-cells = <0>;

		compatible = "ti,omap4-dpll-core-clock";

		clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;

		clocks = <&sys_clkin1>, <&dpll_core_byp_mux>;

		reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>;

	};
@@ -309,10 +317,18 @@ 
		clock-div = <1>;

	};



	dpll_dsp_byp_mux: dpll_dsp_byp_mux {

		#clock-cells = <0>;

		compatible = "ti,mux-clock";

		clocks = <&sys_clkin1>, <&dsp_dpll_hs_clk_div>;

		ti,bit-shift = <23>;

		reg = <0x0240>;

	};



	dpll_dsp_ck: dpll_dsp_ck {

		#clock-cells = <0>;

		compatible = "ti,omap4-dpll-clock";

		clocks = <&sys_clkin1>, <&dsp_dpll_hs_clk_div>;

		clocks = <&sys_clkin1>, <&dpll_dsp_byp_mux>;

		reg = <0x0234>, <0x0238>, <0x0240>, <0x023c>;

	};
@@ -335,10 +351,18 @@ 
		clock-div = <1>;

	};



	dpll_iva_byp_mux: dpll_iva_byp_mux {

		#clock-cells = <0>;

		compatible = "ti,mux-clock";

		clocks = <&sys_clkin1>, <&iva_dpll_hs_clk_div>;

		ti,bit-shift = <23>;

		reg = <0x01ac>;

	};



	dpll_iva_ck: dpll_iva_ck {

		#clock-cells = <0>;

		compatible = "ti,omap4-dpll-clock";

		clocks = <&sys_clkin1>, <&iva_dpll_hs_clk_div>;

		clocks = <&sys_clkin1>, <&dpll_iva_byp_mux>;

		reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>;

	};
@@ -361,10 +385,18 @@ 
		clock-div = <1>;

	};



	dpll_gpu_byp_mux: dpll_gpu_byp_mux {

		#clock-cells = <0>;

		compatible = "ti,mux-clock";

		clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;

		ti,bit-shift = <23>;

		reg = <0x02e4>;

	};



	dpll_gpu_ck: dpll_gpu_ck {

		#clock-cells = <0>;

		compatible = "ti,omap4-dpll-clock";

		clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;

		clocks = <&sys_clkin1>, <&dpll_gpu_byp_mux>;

		reg = <0x02d8>, <0x02dc>, <0x02e4>, <0x02e0>;

	};
@@ -398,10 +430,18 @@ 
		clock-div = <1>;

	};



	dpll_ddr_byp_mux: dpll_ddr_byp_mux {

		#clock-cells = <0>;

		compatible = "ti,mux-clock";

		clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;

		ti,bit-shift = <23>;

		reg = <0x021c>;

	};



	dpll_ddr_ck: dpll_ddr_ck {

		#clock-cells = <0>;

		compatible = "ti,omap4-dpll-clock";

		clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;

		clocks = <&sys_clkin1>, <&dpll_ddr_byp_mux>;

		reg = <0x0210>, <0x0214>, <0x021c>, <0x0218>;

	};
@@ -416,10 +456,18 @@ 
		ti,invert-autoidle-bit;

	};



	dpll_gmac_byp_mux: dpll_gmac_byp_mux {

		#clock-cells = <0>;

		compatible = "ti,mux-clock";

		clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;

		ti,bit-shift = <23>;

		reg = <0x02b4>;

	};



	dpll_gmac_ck: dpll_gmac_ck {

		#clock-cells = <0>;

		compatible = "ti,omap4-dpll-clock";

		clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;

		clocks = <&sys_clkin1>, <&dpll_gmac_byp_mux>;

		reg = <0x02a8>, <0x02ac>, <0x02b4>, <0x02b0>;

	};
@@ -482,10 +530,18 @@ 
		clock-div = <1>;

	};



	dpll_eve_byp_mux: dpll_eve_byp_mux {

		#clock-cells = <0>;

		compatible = "ti,mux-clock";

		clocks = <&sys_clkin1>, <&eve_dpll_hs_clk_div>;

		ti,bit-shift = <23>;

		reg = <0x0290>;

	};



	dpll_eve_ck: dpll_eve_ck {

		#clock-cells = <0>;

		compatible = "ti,omap4-dpll-clock";

		clocks = <&sys_clkin1>, <&eve_dpll_hs_clk_div>;

		clocks = <&sys_clkin1>, <&dpll_eve_byp_mux>;

		reg = <0x0284>, <0x0288>, <0x0290>, <0x028c>;

	};
@@ -1249,10 +1305,18 @@ 
		clock-div = <1>;

	};



	dpll_per_byp_mux: dpll_per_byp_mux {

		#clock-cells = <0>;

		compatible = "ti,mux-clock";

		clocks = <&sys_clkin1>, <&per_dpll_hs_clk_div>;

		ti,bit-shift = <23>;

		reg = <0x014c>;

	};



	dpll_per_ck: dpll_per_ck {

		#clock-cells = <0>;

		compatible = "ti,omap4-dpll-clock";

		clocks = <&sys_clkin1>, <&per_dpll_hs_clk_div>;

		clocks = <&sys_clkin1>, <&dpll_per_byp_mux>;

		reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>;

	};
@@ -1275,10 +1339,18 @@ 
		clock-div = <1>;

	};



	dpll_usb_byp_mux: dpll_usb_byp_mux {

		#clock-cells = <0>;

		compatible = "ti,mux-clock";

		clocks = <&sys_clkin1>, <&usb_dpll_hs_clk_div>;

		ti,bit-shift = <23>;

		reg = <0x018c>;

	};



	dpll_usb_ck: dpll_usb_ck {

		#clock-cells = <0>;

		compatible = "ti,omap4-dpll-j-type-clock";

		clocks = <&sys_clkin1>, <&usb_dpll_hs_clk_div>;

		clocks = <&sys_clkin1>, <&dpll_usb_byp_mux>;

		reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>;

	};

arch/arm/boot/dts/imx6qdl-sabresd.dtsi

+2 −0
Original line number Diff line number Diff line
@@ -35,6 +35,7 @@ 
			regulator-max-microvolt = <5000000>;

			gpio = <&gpio3 22 0>;

			enable-active-high;

			vin-supply = <&swbst_reg>;

		};



		reg_usb_h1_vbus: regulator@1 {
@@ -45,6 +46,7 @@ 
			regulator-max-microvolt = <5000000>;

			gpio = <&gpio1 29 0>;

			enable-active-high;

			vin-supply = <&swbst_reg>;

		};



		reg_audio: regulator@2 {