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Commit 003dbd81 authored by Jaydeep Sen's avatar Jaydeep Sen Committed by Gerrit - the friendly Code Review server
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clk: msm: msm8937: Enable using sleep_vote for gpll0 



Introduce a new clock as gpll0_sleep_clk_src as parent of gpll0_clk_src
which is used by all non-cpu clients in HLOS. This sleep clock will clear
the sleep bit for gpll0 when enabled and set the sleep bit when disabled.
Thus it is ensured that GPLL0 sleep-vote is set only when there is no
client in HLOS using it.

Change-Id: Ifab19eb6455269eb6b19223c1ae402701cbe1e91
Signed-off-by: default avatarJaydeep Sen <jsen@codeaurora.org>
parent 1cc91fb7

drivers/clk/msm/clock-gcc-8952.c

+17 −1
Original line number Diff line number Diff line
@@ -288,6 +288,21 @@ static struct pll_clk a53ss_c1_pll = { 
	},

};



static struct pll_vote_clk gpll0_sleep_clk_src = {

	.en_reg = (void __iomem *)APCS_CLOCK_SLEEP_ENA_VOTE,

	.en_mask = BIT(23),

	.status_reg = (void __iomem *)GPLL0_MODE,

	.status_mask = BIT(30),

	.base = &virt_bases[GCC_BASE],

	.c = {

		.parent = &xo_clk_src.c,

		.rate = 800000000,

		.dbg_name = "gpll0_sleep_clk_src",

		.ops = &clk_ops_pll_sleep_vote,

		CLK_INIT(gpll0_sleep_clk_src.c),

	},

};



static unsigned int soft_vote_gpll0;



/* PLL_ACTIVE_FLAG bit of GCC_GPLL0_MODE register
@@ -320,7 +335,7 @@ static struct pll_vote_clk gpll0_clk_src_8937 = { 
	.soft_vote_mask = PLL_SOFT_VOTE_PRIMARY,

	.base = &virt_bases[GCC_BASE],

	.c = {

		.parent = &xo_clk_src.c,

		.parent = &gpll0_sleep_clk_src.c,

		.rate = 800000000,

		.dbg_name = "gpll0_clk_src_8937",

		.ops = &clk_ops_pll_acpu_vote,
@@ -3841,6 +3856,7 @@ static struct clk_lookup msm_clocks_lookup_8952[] = { 
static struct clk_lookup msm_clocks_lookup_8937[] = {

	CLK_LIST(gpll0_clk_src_8937),

	CLK_LIST(gpll0_ao_clk_src_8937),

	CLK_LIST(gpll0_sleep_clk_src),

	CLK_LIST(esc1_clk_src),

	CLK_LIST(gcc_mdss_esc1_clk),

	CLK_LIST(gcc_dcc_clk),

include/dt-bindings/clock/msm-clocks-8952.h

+1 −0
Original line number Diff line number Diff line
@@ -22,6 +22,7 @@ 
#define clk_gpll0_ao_clk_src_8937		0x923c7546

#define clk_gpll0_clk_src			0x5933b69f

#define clk_gpll0_ao_clk_src			0x6b2fb034

#define clk_gpll0_sleep_clk_src			0x4f89fcf0

#define clk_gpll0_out_main			0x850fecec

#define clk_gpll0_out_aux			0x64e55d63

#define clk_gpll0_misc				0xe06ee816

include/dt-bindings/clock/msm-clocks-hwio-8952.h

+1 −0
Original line number Diff line number Diff line
@@ -212,6 +212,7 @@ 
#define SYSTEM_MM_NOC_CMD_RCGR		0x3D000

#define USB_FS_BCR			0x3F000



#define APCS_CLOCK_SLEEP_ENA_VOTE	0x45008

#define BYTE1_CMD_RCGR			0x4D0B0

#define ESC1_CMD_RCGR			0x4D0A8

#define PCLK1_CMD_RCGR			0x4D0B8