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Commit 0017f447 authored by Joseph Lo's avatar Joseph Lo Committed by Stephen Warren
Browse files

clk: tegra114: add LP1 suspend/resume support 



When the system suspends to LP1, the CPU clock source is switched to
CLK_M (12MHz Oscillator) during suspend/resume flow. The CPU clock
source is controlled by the CCLKG_BURST_POLICY register, and hence this
register must be restored during LP1 resume.

Cc: Mike Turquette <mturquette@linaro.org>
Signed-off-by: default avatarJoseph Lo <josephl@nvidia.com>
Signed-off-by: default avatarStephen Warren <swarren@nvidia.com>
parent 444f9a80

drivers/clk/tegra/clk-tegra114.c

+12 −0
Original line number Diff line number Diff line
@@ -293,6 +293,8 @@ 
#ifdef CONFIG_PM_SLEEP

static struct cpu_clk_suspend_context {

	u32 clk_csite_src;

	u32 cclkg_burst;

	u32 cclkg_divider;

} tegra114_cpu_clk_sctx;

#endif
@@ -2155,12 +2157,22 @@ static void tegra114_cpu_clock_suspend(void) 
	tegra114_cpu_clk_sctx.clk_csite_src =

				readl(clk_base + CLK_SOURCE_CSITE);

	writel(3 << 30, clk_base + CLK_SOURCE_CSITE);



	tegra114_cpu_clk_sctx.cclkg_burst =

				readl(clk_base + CCLKG_BURST_POLICY);

	tegra114_cpu_clk_sctx.cclkg_divider =

				readl(clk_base + CCLKG_BURST_POLICY + 4);

}



static void tegra114_cpu_clock_resume(void)

{

	writel(tegra114_cpu_clk_sctx.clk_csite_src,

					clk_base + CLK_SOURCE_CSITE);



	writel(tegra114_cpu_clk_sctx.cclkg_burst,

					clk_base + CCLKG_BURST_POLICY);

	writel(tegra114_cpu_clk_sctx.cclkg_divider,

					clk_base + CCLKG_BURST_POLICY + 4);

}

#endif