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Commit fd6b8f43 authored by Tvrtko Ursulin's avatar Tvrtko Ursulin
Browse files

drm/i915: Make IS_IVYBRIDGE only take dev_priv 



Saves 848 bytes of .rodata strings.

v2: Add parantheses around dev_priv. (Ville Syrjala)
v3: Rebase.

Signed-off-by: default avatarTvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: default avatarDavid Weinehall <david.weinehall@linux.intel.com>
Acked-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
Acked-by: default avatarJani Nikula <jani.nikula@linux.intel.com>
Acked-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Acked-by: default avatarMaarten Lankhorst <maarten.lankhorst@linux.intel.com>
parent 50a0bc90

drivers/gpu/drm/i915/i915_drv.c

+11 −8
Original line number Diff line number Diff line
@@ -114,7 +114,7 @@ static bool i915_error_injected(struct drm_i915_private *dev_priv) 
		      fmt, ##__VA_ARGS__)





static enum intel_pch intel_virt_detect_pch(struct drm_device *dev)

static enum intel_pch intel_virt_detect_pch(struct drm_i915_private *dev_priv)

{

	enum intel_pch ret = PCH_NOP;
@@ -125,16 +125,16 @@ static enum intel_pch intel_virt_detect_pch(struct drm_device *dev) 
	 * make an educated guess as to which PCH is really there.

	 */



	if (IS_GEN5(dev)) {

	if (IS_GEN5(dev_priv)) {

		ret = PCH_IBX;

		DRM_DEBUG_KMS("Assuming Ibex Peak PCH\n");

	} else if (IS_GEN6(dev) || IS_IVYBRIDGE(dev)) {

	} else if (IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv)) {

		ret = PCH_CPT;

		DRM_DEBUG_KMS("Assuming CouarPoint PCH\n");

	} else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {

	} else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {

		ret = PCH_LPT;

		DRM_DEBUG_KMS("Assuming LynxPoint PCH\n");

	} else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {

	} else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {

		ret = PCH_SPT;

		DRM_DEBUG_KMS("Assuming SunrisePoint PCH\n");

	}
@@ -178,12 +178,14 @@ static void intel_detect_pch(struct drm_device *dev) 
			} else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {

				dev_priv->pch_type = PCH_CPT;

				DRM_DEBUG_KMS("Found CougarPoint PCH\n");

				WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));

				WARN_ON(!(IS_GEN6(dev_priv) ||

					IS_IVYBRIDGE(dev_priv)));

			} else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {

				/* PantherPoint is CPT compatible */

				dev_priv->pch_type = PCH_CPT;

				DRM_DEBUG_KMS("Found PantherPoint PCH\n");

				WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));

				WARN_ON(!(IS_GEN6(dev_priv) ||

					IS_IVYBRIDGE(dev_priv)));

			} else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {

				dev_priv->pch_type = PCH_LPT;

				DRM_DEBUG_KMS("Found LynxPoint PCH\n");
@@ -217,7 +219,8 @@ static void intel_detect_pch(struct drm_device *dev) 
					    PCI_SUBVENDOR_ID_REDHAT_QUMRANET &&

				    pch->subsystem_device ==

					    PCI_SUBDEVICE_ID_QEMU)) {

				dev_priv->pch_type = intel_virt_detect_pch(dev);

				dev_priv->pch_type =

					intel_virt_detect_pch(dev_priv);

			} else

				continue;

drivers/gpu/drm/i915/i915_drv.h

+1 −1
Original line number Diff line number Diff line
@@ -2651,7 +2651,7 @@ struct drm_i915_cmd_table { 
#define IS_PINEVIEW(dev)	(INTEL_INFO(dev)->is_pineview)

#define IS_G33(dev)		(INTEL_INFO(dev)->is_g33)

#define IS_IRONLAKE_M(dev_priv)	(INTEL_DEVID(dev_priv) == 0x0046)

#define IS_IVYBRIDGE(dev)	(INTEL_INFO(dev)->is_ivybridge)

#define IS_IVYBRIDGE(dev_priv)	((dev_priv)->info.is_ivybridge)

#define IS_IVB_GT1(dev_priv)	(INTEL_DEVID(dev_priv) == 0x0156 || \

				 INTEL_DEVID(dev_priv) == 0x0152 || \

				 INTEL_DEVID(dev_priv) == 0x015a)

drivers/gpu/drm/i915/i915_gem.c

+1 −1
Original line number Diff line number Diff line
@@ -4432,7 +4432,7 @@ i915_gem_init_hw(struct drm_device *dev) 
			   LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);



	if (HAS_PCH_NOP(dev_priv)) {

		if (IS_IVYBRIDGE(dev)) {

		if (IS_IVYBRIDGE(dev_priv)) {

			u32 temp = I915_READ(GEN7_MSG_CTL);

			temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);

			I915_WRITE(GEN7_MSG_CTL, temp);

drivers/gpu/drm/i915/i915_gem_context.c

+1 −1
Original line number Diff line number Diff line
@@ -192,7 +192,7 @@ i915_gem_alloc_context_obj(struct drm_device *dev, size_t size) 
	 * This is only applicable for Ivy Bridge devices since

	 * later platforms don't have L3 control bits in the PTE.

	 */

	if (IS_IVYBRIDGE(dev)) {

	if (IS_IVYBRIDGE(to_i915(dev))) {

		ret = i915_gem_object_set_cache_level(obj, I915_CACHE_L3_LLC);

		/* Failure shouldn't ever happen this early */

		if (WARN_ON(ret)) {

drivers/gpu/drm/i915/intel_display.c

+6 −6
Original line number Diff line number Diff line
@@ -3727,7 +3727,7 @@ static void intel_fdi_normal_train(struct drm_crtc *crtc) 
	/* enable normal train */

	reg = FDI_TX_CTL(pipe);

	temp = I915_READ(reg);

	if (IS_IVYBRIDGE(dev)) {

	if (IS_IVYBRIDGE(dev_priv)) {

		temp &= ~FDI_LINK_TRAIN_NONE_IVB;

		temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;

	} else {
@@ -3752,7 +3752,7 @@ static void intel_fdi_normal_train(struct drm_crtc *crtc) 
	udelay(1000);



	/* IVB wants error correction enabled */

	if (IS_IVYBRIDGE(dev))

	if (IS_IVYBRIDGE(dev_priv))

		I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |

			   FDI_FE_ERRC_ENABLE);

}
@@ -4538,7 +4538,7 @@ static void ironlake_pch_enable(struct drm_crtc *crtc) 


	assert_pch_transcoder_disabled(dev_priv, pipe);



	if (IS_IVYBRIDGE(dev))

	if (IS_IVYBRIDGE(dev_priv))

		ivybridge_update_fdi_bc_bifurcation(intel_crtc);



	/* Write the TU size bits before fdi link training, so that error
@@ -4852,7 +4852,7 @@ static void ironlake_pfit_enable(struct intel_crtc *crtc) 
		 * as some pre-programmed values are broken,

		 * e.g. x201.

		 */

		if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))

		if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv))

			I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |

						 PF_PIPE_SEL_IVB(pipe));

		else
@@ -12249,7 +12249,7 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc, 
		if (fb->modifier[0] != old_fb->modifier[0])

			/* vlv: DISPLAY_FLIP fails to change tiling */

			engine = NULL;

	} else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {

	} else if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) {

		engine = dev_priv->engine[BCS];

	} else if (INTEL_INFO(dev)->gen >= 7) {

		engine = i915_gem_active_get_engine(&obj->last_write,
@@ -12525,7 +12525,7 @@ int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state, 
	 * cstate->update_wm was already set above, so this flag will

	 * take effect when we commit and program watermarks.

	 */

	if (plane->type == DRM_PLANE_TYPE_OVERLAY && IS_IVYBRIDGE(dev) &&

	if (plane->type == DRM_PLANE_TYPE_OVERLAY && IS_IVYBRIDGE(dev_priv) &&

	    needs_scaling(to_intel_plane_state(plane_state)) &&

	    !needs_scaling(old_plane_state))

		pipe_config->disable_lp_wm = true;