Loading arch/arc/mm/cache.c +5 −1 Original line number Diff line number Diff line Loading @@ -271,7 +271,11 @@ void __cache_line_loop_v2(phys_addr_t paddr, unsigned long vaddr, /* * For ARC700 MMUv3 I-cache and D-cache flushes * Also reused for HS38 aliasing I-cache configuration * - ARC700 programming model requires paddr and vaddr be passed in seperate * AUX registers (*_IV*L and *_PTAG respectively) irrespective of whether the * caches actually alias or not. * - For HS38, only the aliasing I-cache configuration uses the PTAG reg * (non aliasing I-cache version doesn't; while D-cache can't possibly alias) */ static inline void __cache_line_loop_v3(phys_addr_t paddr, unsigned long vaddr, Loading Loading
arch/arc/mm/cache.c +5 −1 Original line number Diff line number Diff line Loading @@ -271,7 +271,11 @@ void __cache_line_loop_v2(phys_addr_t paddr, unsigned long vaddr, /* * For ARC700 MMUv3 I-cache and D-cache flushes * Also reused for HS38 aliasing I-cache configuration * - ARC700 programming model requires paddr and vaddr be passed in seperate * AUX registers (*_IV*L and *_PTAG respectively) irrespective of whether the * caches actually alias or not. * - For HS38, only the aliasing I-cache configuration uses the PTAG reg * (non aliasing I-cache version doesn't; while D-cache can't possibly alias) */ static inline void __cache_line_loop_v3(phys_addr_t paddr, unsigned long vaddr, Loading
Vineet Gupta <vgupta@synopsys.com>Vineet Gupta <vgupta@synopsys.com>