Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit f8fa4811 authored by Steven J. Hill's avatar Steven J. Hill Committed by John Crispin
Browse files

MIPS: Add support for the M14KEc core. 



Signed-off-by: default avatarSteven J. Hill <sjhill@mips.com>
Patchwork: http://patchwork.linux-mips.org/patch/4682/


Signed-off-by: default avatarJohn Crispin <blogic@openwrt.org>
parent 127993e5

arch/mips/include/asm/cpu-features.h

+3 −0
Original line number Diff line number Diff line
@@ -98,6 +98,9 @@ 
#ifndef cpu_has_rixi

#define cpu_has_rixi		(cpu_data[0].options & MIPS_CPU_RIXI)

#endif

#ifndef cpu_has_mmips

#define cpu_has_mmips		(cpu_data[0].options & MIPS_CPU_MICROMIPS)

#endif

#ifndef cpu_has_vtag_icache

#define cpu_has_vtag_icache	(cpu_data[0].icache.flags & MIPS_CACHE_VTAG)

#endif

arch/mips/include/asm/cpu.h

+3 −0
Original line number Diff line number Diff line
@@ -96,6 +96,7 @@ 
#define PRID_IMP_1004K		0x9900

#define PRID_IMP_1074K		0x9a00

#define PRID_IMP_M14KC		0x9c00

#define PRID_IMP_M14KEC		0x9e00



/*

 * These are the PRID's for when 23:16 == PRID_COMP_SIBYTE
@@ -264,6 +265,7 @@ enum cpu_type_enum { 
	CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K,

	CPU_ALCHEMY, CPU_PR4450, CPU_BMIPS32, CPU_BMIPS3300, CPU_BMIPS4350,

	CPU_BMIPS4380, CPU_BMIPS5000, CPU_JZRISC, CPU_LOONGSON1, CPU_M14KC,

	CPU_M14KEC,



	/*

	 * MIPS64 class processors
@@ -322,6 +324,7 @@ enum cpu_type_enum { 
#define MIPS_CPU_ULRI		0x00200000 /* CPU has ULRI feature */

#define MIPS_CPU_PCI		0x00400000 /* CPU has Perf Ctr Int indicator */

#define MIPS_CPU_RIXI		0x00800000 /* CPU has TLB Read/eXec Inhibit */

#define MIPS_CPU_MICROMIPS	0x01000000 /* CPU has microMIPS capability */



/*

 * CPU ASE encodings

arch/mips/include/asm/mipsregs.h

+1 −0
Original line number Diff line number Diff line
@@ -595,6 +595,7 @@ 
#define MIPS_CONF3_DSP2P	(_ULCAST_(1) << 11)

#define MIPS_CONF3_RXI		(_ULCAST_(1) << 12)

#define MIPS_CONF3_ULRI		(_ULCAST_(1) << 13)

#define MIPS_CONF3_ISA		(_ULCAST_(3) << 14)



#define MIPS_CONF4_MMUSIZEEXT	(_ULCAST_(255) << 0)

#define MIPS_CONF4_MMUEXTDEF	(_ULCAST_(3) << 14)

arch/mips/kernel/cpu-probe.c

+7 −0
Original line number Diff line number Diff line
@@ -201,6 +201,7 @@ void __init check_wait(void) 
		break;



	case CPU_M14KC:

	case CPU_M14KEC:

	case CPU_24K:

	case CPU_34K:

	case CPU_1004K:
@@ -439,6 +440,8 @@ static inline unsigned int decode_config3(struct cpuinfo_mips *c) 
		c->ases |= MIPS_ASE_MIPSMT;

	if (config3 & MIPS_CONF3_ULRI)

		c->options |= MIPS_CPU_ULRI;

	if (config3 & MIPS_CONF3_ISA)

		c->options |= MIPS_CPU_MICROMIPS;



	return config3 & MIPS_CONF_M;

}
@@ -861,6 +864,10 @@ static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu) 
		c->cputype = CPU_M14KC;

		__cpu_name[cpu] = "MIPS M14Kc";

		break;

	case PRID_IMP_M14KEC:

		c->cputype = CPU_M14KEC;

		__cpu_name[cpu] = "MIPS M14KEc";

		break;

	case PRID_IMP_1004K:

		c->cputype = CPU_1004K;

		__cpu_name[cpu] = "MIPS 1004Kc";

arch/mips/kernel/proc.c

+1 −0
Original line number Diff line number Diff line
@@ -73,6 +73,7 @@ static int show_cpuinfo(struct seq_file *m, void *v) 
	if (cpu_has_dsp)	seq_printf(m, "%s", " dsp");

	if (cpu_has_dsp2)	seq_printf(m, "%s", " dsp2");

	if (cpu_has_mipsmt)	seq_printf(m, "%s", " mt");

	if (cpu_has_mmips)	seq_printf(m, "%s", " micromips");

	seq_printf(m, "\n");



	seq_printf(m, "shadow register sets\t: %d\n",