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Commit f60a2abf authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux 

Pull clk updates from Stephen Boyd:
 "The diff is dominated by the Allwinner A10/A20 SoCs getting converted
  to the sunxi-ng framework. Otherwise, the heavy hitters are various
  drivers for SoCs like AT91, Amlogic, Renesas, and Rockchip. There are
  some other new clk drivers in here too but overall this is just a
  bunch of clk drivers for various different pieces of hardware and a
  collection of non-critical fixes for clk drivers.

  New Drivers:
   - Allwinner R40 SoCs
   - Renesas R-Car Gen3 USB 2.0 clock selector PHY
   - Atmel AT91 audio PLL
   - Uniphier PXs3 SoCs
   - ARC HSDK Board PLLs
   - AXS10X Board PLLs
   - STMicroelectronics STM32H743 SoCs

  Removed Drivers:
   - Non-compiling mb86s7x support

  Updates:
   - Allwinner A10/A20 SoCs converted to sunxi-ng framework
   - Allwinner H3 CPU clk fixes
   - Renesas R-Car D3 SoC
   - Renesas V2H and M3-W modules
   - Samsung Exynos5420/5422/5800 audio fixes
   - Rockchip fractional clk approximation fixes
   - Rockchip rk3126 SoC support within the rk3128 driver
   - Amlogic gxbb CEC32 and sd_emmc clks
   - Amlogic meson8b reset controller support
   - IDT VersaClock 5P49V5925/5P49V6901 support
   - Qualcomm MSM8996 SMMU clks
   - Various 'const' applications for struct clk_ops
   - si5351 PLL reset bugfix
   - Uniphier audio on LD11/LD20 and ethernet support on LD11/LD20/Pro4/PXs2
   - Assorted Tegra clk driver fixes"

* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (120 commits)
  clk: si5351: fix PLL reset
  ASoC: atmel-classd: remove aclk clock
  ASoC: atmel-classd: remove aclk clock from DT binding
  clk: at91: clk-generated: make gclk determine audio_pll rate
  clk: at91: clk-generated: create function to find best_diff
  clk: at91: add audio pll clock drivers
  dt-bindings: clk: at91: add audio plls to the compatible list
  clk: at91: clk-generated: remove useless divisor loop
  clk: mb86s7x: Drop non-building driver
  clk: ti: check for null return in strrchr to avoid null dereferencing
  clk: Don't write error code into divider register
  clk: uniphier: add video input subsystem clock
  clk: uniphier: add audio system clock
  clk: stm32h7: Add stm32h743 clock driver
  clk: gate: expose clk_gate_ops::is_enabled
  clk: nxp: clk-lpc32xx: rename clk_gate_is_enabled()
  clk: uniphier: add PXs3 clock data
  clk: hi6220: change watchdog clock source
  clk: Kconfig: Name RK805 in Kconfig for COMMON_CLK_RK808
  clk: cs2000: Add cs2000_set_saved_rate
  ...
parents 561a8eb3 73c950da

Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.txt

+16 −6
Original line number Diff line number Diff line
@@ -5,9 +5,11 @@ controllers within the Always-On part of the SoC. 


Required Properties:



- compatible: should be "amlogic,gxbb-aoclkc"

- reg: physical base address of the clock controller and length of memory

       mapped region.

- compatible: value should be different for each SoC family as :

	- GXBB (S905) : "amlogic,meson-gxbb-aoclkc"

	- GXL (S905X, S905D) : "amlogic,meson-gxl-aoclkc"

	- GXM (S912) : "amlogic,meson-gxm-aoclkc"

	followed by the common "amlogic,meson-gx-aoclkc"



- #clock-cells: should be 1.
@@ -23,14 +25,22 @@ to specify the reset which they consume. All available resets are defined as 
preprocessor macros in the dt-bindings/reset/gxbb-aoclkc.h header and can be

used in device tree sources.



Parent node should have the following properties :

- compatible: "amlogic,meson-gx-ao-sysctrl", "syscon", "simple-mfd"

- reg: base address and size of the AO system control register space.



Example: AO Clock controller node:



	clkc_AO: clock-controller@040 {

		compatible = "amlogic,gxbb-aoclkc";

		reg = <0x0 0x040 0x0 0x4>;

ao_sysctrl: sys-ctrl@0 {

	compatible = "amlogic,meson-gx-ao-sysctrl", "syscon", "simple-mfd";

	reg =  <0x0 0x0 0x0 0x100>;



	clkc_AO: clock-controller {

		compatible = "amlogic,meson-gxbb-aoclkc", "amlogic,meson-gx-aoclkc";

		#clock-cells = <1>;

		#reset-cells = <1>;

	};

};



Example: UART controller node that consumes the clock and reset generated

  by the clock controller:

Documentation/devicetree/bindings/clock/at91-clock.txt

+10 −0
Original line number Diff line number Diff line
@@ -81,6 +81,16 @@ Required properties: 
	"atmel,sama5d2-clk-generated":

		at91 generated clock



	"atmel,sama5d2-clk-audio-pll-frac":

		at91 audio fractional pll



	"atmel,sama5d2-clk-audio-pll-pad":

		at91 audio pll CLK_AUDIO output pin



	"atmel,sama5d2-clk-audio-pll-pmc"

		at91 audio pll output on AUDIOPLLCLK that feeds the PMC

		and can be used by peripheral clock or generic clock



Required properties for SCKC node:

- reg : defines the IO memory reserved for the SCKC.

- #size-cells : shall be 0 (reg is used to encode clk id).

Documentation/devicetree/bindings/clock/idt,versaclock5.txt

+23 −7
Original line number Diff line number Diff line 
Binding for IDT VersaClock5 programmable i2c clock generator.

Binding for IDT VersaClock 5,6 programmable i2c clock generators.



The IDT VersaClock5 are programmable i2c clock generators providing

from 3 to 12 output clocks.

The IDT VersaClock 5 and VersaClock 6 are programmable i2c clock

generators providing from 3 to 12 output clocks.



==I2C device node==



Required properties:

- compatible:	shall be one of "idt,5p49v5923" , "idt,5p49v5933" ,

		"idt,5p49v5935".

- compatible:	shall be one of

		"idt,5p49v5923"

		"idt,5p49v5925"

		"idt,5p49v5933"

		"idt,5p49v5935"

		"idt,5p49v6901"

- reg:		i2c device address, shall be 0x68 or 0x6a.

- #clock-cells:	from common clock binding; shall be set to 1.

- clocks:	from common clock binding; list of parent clock handles,

		- 5p49v5923: (required) either or both of XTAL or CLKIN

		- 5p49v5923 and

		  5p49v5925 and

		  5p49v6901: (required) either or both of XTAL or CLKIN

					reference clock.

		- 5p49v5933 and

		- 5p49v5935: (optional) property not present (internal

					Xtal used) or CLKIN reference

					clock.

- clock-names:	from common clock binding; clock input names, can be

		- 5p49v5923: (required) either or both of "xin", "clkin".

		- 5p49v5923 and

		  5p49v5925 and

		  5p49v6901: (required) either or both of "xin", "clkin".

		- 5p49v5933 and

		- 5p49v5935: (optional) property not present or "clkin".
@@ -37,6 +45,7 @@ clock specifier, the following mapping applies: 
	1 -- OUT1

	2 -- OUT4



5P49V5925 and

5P49V5935:

	0 -- OUT0_SEL_I2CB

	1 -- OUT1
@@ -44,6 +53,13 @@ clock specifier, the following mapping applies: 
	3 -- OUT3

	4 -- OUT4



5P49V6901:

	0 -- OUT0_SEL_I2CB

	1 -- OUT1

	2 -- OUT2

	3 -- OUT3

	4 -- OUT4



==Example==



/* 25MHz reference crystal */

Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt

+2 −1
Original line number Diff line number Diff line
@@ -22,6 +22,7 @@ Required Properties: 
      - "renesas,r8a7794-cpg-mssr" for the r8a7794 SoC (R-Car E2)

      - "renesas,r8a7795-cpg-mssr" for the r8a7795 SoC (R-Car H3)

      - "renesas,r8a7796-cpg-mssr" for the r8a7796 SoC (R-Car M3-W)

      - "renesas,r8a77995-cpg-mssr" for the r8a77995 SoC (R-Car D3)



  - reg: Base address and length of the memory resource used by the CPG/MSSR

    block
@@ -30,7 +31,7 @@ Required Properties: 
    clock-names

  - clock-names: List of external parent clock names. Valid names are:

      - "extal" (r8a7743, r8a7745, r8a7790, r8a7791, r8a7792, r8a7793, r8a7794,

		 r8a7795, r8a7796)

		 r8a7795, r8a7796, r8a77995)

      - "extalr" (r8a7795, r8a7796)

      - "usb_extal" (r8a7743, r8a7745, r8a7790, r8a7791, r8a7793, r8a7794)

Documentation/devicetree/bindings/clock/renesas,rcar-usb2-clock-sel.txt

0 → 100644
+55 −0
Original line number Diff line number Diff line 
* Renesas R-Car USB 2.0 clock selector



This file provides information on what the device node for the R-Car USB 2.0

clock selector.



If you connect an external clock to the USB_EXTAL pin only, you should set

the clock rate to "usb_extal" node only.

If you connect an oscillator to both the USB_XTAL and USB_EXTAL, this module

is not needed because this is default setting. (Of course, you can set the

clock rates to both "usb_extal" and "usb_xtal" nodes.



Case 1: An external clock connects to R-Car SoC

	+----------+   +--- R-Car ---------------------+

	|External  |---|USB_EXTAL ---> all usb channels|

	|clock     |   |USB_XTAL                       |

	+----------+   +-------------------------------+

In this case, we need this driver with "usb_extal" clock.



Case 2: An oscillator connects to R-Car SoC

	+----------+   +--- R-Car ---------------------+

	|Oscillator|---|USB_EXTAL -+-> all usb channels|

	|          |---|USB_XTAL --+                   |

	+----------+   +-------------------------------+

In this case, we don't need this selector.



Required properties:

- compatible: "renesas,r8a7795-rcar-usb2-clock-sel" if the device is a part of

	      an R8A7795 SoC.

	      "renesas,r8a7796-rcar-usb2-clock-sel" if the device if a part of

	      an R8A7796 SoC.

	      "renesas,rcar-gen3-usb2-clock-sel" for a generic R-Car Gen3

	      compatible device.



	      When compatible with the generic version, nodes must list the

	      SoC-specific version corresponding to the platform first

	      followed by the generic version.



- reg: offset and length of the USB 2.0 clock selector register block.

- clocks: A list of phandles and specifier pairs.

- clock-names: Name of the clocks.

 - The functional clock must be "ehci_ohci"

 - The USB_EXTAL clock pin must be "usb_extal"

 - The USB_XTAL clock pin must be "usb_xtal"

- #clock-cells: Must be 0



Example (R-Car H3):



	usb2_clksel: clock-controller@e6590630 {

		compatible = "renesas,r8a77950-rcar-usb2-clock-sel",

			     "renesas,rcar-gen3-usb2-clock-sel";

		reg = <0 0xe6590630 0 0x02>;

		clocks = <&cpg CPG_MOD 703>, <&usb_extal>, <&usb_xtal>;

		clock-names = "ehci_ohci", "usb_extal", "usb_xtal";

		#clock-cells = <0>;

	};