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Commit f31e4b6f authored by Anirudh Venkataramanan's avatar Anirudh Venkataramanan Committed by Jeff Kirsher
Browse files

ice: Start hardware initialization 



This patch implements multiple pieces of the initialization flow
as follows:

1) A reset is issued to ensure a clean device state, followed
   by initialization of admin queue interface.

2) Once the admin queue interface is up, clear the PF config
   and transition the device to non-PXE mode.

3) Get the NVM configuration stored in the device's non-volatile
   memory (NVM) using ice_init_nvm.

CC: Shannon Nelson <shannon.nelson@oracle.com>
Signed-off-by: default avatarAnirudh Venkataramanan <anirudh.venkataramanan@intel.com>
Acked-by: default avatarShannon Nelson <shannon.nelson@oracle.com>
Tested-by: default avatarTony Brelinski <tonyx.brelinski@intel.com>
Signed-off-by: default avatarJeff Kirsher <jeffrey.t.kirsher@intel.com>
parent 7ec59eea

drivers/net/ethernet/intel/ice/Makefile

+2 −1
Original line number Original line Diff line number Diff line
@@ -9,4 +9,5 @@ obj-$(CONFIG_ICE) += ice.o 




ice-y := ice_main.o	\

ice-y := ice_main.o	\

	 ice_controlq.o	\

	 ice_controlq.o	\

	 ice_common.o
 
	 ice_common.o	\

	 ice_nvm.o

drivers/net/ethernet/intel/ice/ice.h

+2 −0
Original line number Original line Diff line number Diff line
@@ -16,8 +16,10 @@ 
#include <linux/bitmap.h>

#include <linux/bitmap.h>

#include "ice_devids.h"

#include "ice_devids.h"

#include "ice_type.h"

#include "ice_type.h"

#include "ice_common.h"





#define ICE_BAR0		0

#define ICE_BAR0		0

#define ICE_AQ_LEN		64





#define ICE_DFLT_NETIF_M (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)

#define ICE_DFLT_NETIF_M (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)

drivers/net/ethernet/intel/ice/ice_adminq_cmd.h

+79 −0
Original line number Original line Diff line number Diff line
@@ -36,6 +36,67 @@ struct ice_aqc_q_shutdown { 
	u8 reserved[12];

	u8 reserved[12];

};

};





/* Request resource ownership (direct 0x0008)

 * Release resource ownership (direct 0x0009)

 */

struct ice_aqc_req_res {

	__le16 res_id;

#define ICE_AQC_RES_ID_NVM		1

#define ICE_AQC_RES_ID_SDP		2

#define ICE_AQC_RES_ID_CHNG_LOCK	3

#define ICE_AQC_RES_ID_GLBL_LOCK	4

	__le16 access_type;

#define ICE_AQC_RES_ACCESS_READ		1

#define ICE_AQC_RES_ACCESS_WRITE	2



	/* Upon successful completion, FW writes this value and driver is

	 * expected to release resource before timeout. This value is provided

	 * in milliseconds.

	 */

	__le32 timeout;

#define ICE_AQ_RES_NVM_READ_DFLT_TIMEOUT_MS	3000

#define ICE_AQ_RES_NVM_WRITE_DFLT_TIMEOUT_MS	180000

#define ICE_AQ_RES_CHNG_LOCK_DFLT_TIMEOUT_MS	1000

#define ICE_AQ_RES_GLBL_LOCK_DFLT_TIMEOUT_MS	3000

	/* For SDP: pin id of the SDP */

	__le32 res_number;

	/* Status is only used for ICE_AQC_RES_ID_GLBL_LOCK */

	__le16 status;

#define ICE_AQ_RES_GLBL_SUCCESS		0

#define ICE_AQ_RES_GLBL_IN_PROG		1

#define ICE_AQ_RES_GLBL_DONE		2

	u8 reserved[2];

};



/* Clear PXE Command and response (direct 0x0110) */

struct ice_aqc_clear_pxe {

	u8 rx_cnt;

#define ICE_AQC_CLEAR_PXE_RX_CNT		0x2

	u8 reserved[15];

};



/* NVM Read command (indirect 0x0701)

 * NVM Erase commands (direct 0x0702)

 * NVM Update commands (indirect 0x0703)

 */

struct ice_aqc_nvm {

	u8	cmd_flags;

#define ICE_AQC_NVM_LAST_CMD		BIT(0)

#define ICE_AQC_NVM_PCIR_REQ		BIT(0)	/* Used by NVM Update reply */

#define ICE_AQC_NVM_PRESERVATION_S	1

#define ICE_AQC_NVM_PRESERVATION_M	(3 << CSR_AQ_NVM_PRESERVATION_S)

#define ICE_AQC_NVM_NO_PRESERVATION	(0 << CSR_AQ_NVM_PRESERVATION_S)

#define ICE_AQC_NVM_PRESERVE_ALL	BIT(1)

#define ICE_AQC_NVM_PRESERVE_SELECTED	(3 << CSR_AQ_NVM_PRESERVATION_S)

#define ICE_AQC_NVM_FLASH_ONLY		BIT(7)

	u8	module_typeid;

	__le16	length;

#define ICE_AQC_NVM_ERASE_LEN	0xFFFF

	__le32	offset;

	__le32	addr_high;

	__le32	addr_low;

};



/**

/**

 * struct ice_aq_desc - Admin Queue (AQ) descriptor

 * struct ice_aq_desc - Admin Queue (AQ) descriptor

 * @flags: ICE_AQ_FLAG_* flags

 * @flags: ICE_AQ_FLAG_* flags
@@ -65,6 +126,9 @@ struct ice_aq_desc { 
		struct ice_aqc_generic generic;

		struct ice_aqc_generic generic;

		struct ice_aqc_get_ver get_ver;

		struct ice_aqc_get_ver get_ver;

		struct ice_aqc_q_shutdown q_shutdown;

		struct ice_aqc_q_shutdown q_shutdown;

		struct ice_aqc_req_res res_owner;

		struct ice_aqc_clear_pxe clear_pxe;

		struct ice_aqc_nvm nvm;

	} params;

	} params;

};

};
@@ -82,6 +146,8 @@ struct ice_aq_desc { 
/* error codes */

/* error codes */

enum ice_aq_err {

enum ice_aq_err {

	ICE_AQ_RC_OK		= 0,  /* success */

	ICE_AQ_RC_OK		= 0,  /* success */

	ICE_AQ_RC_EBUSY		= 12, /* Device or resource busy */

	ICE_AQ_RC_EEXIST	= 13, /* object already exists */

};

};





/* Admin Queue command opcodes */

/* Admin Queue command opcodes */
@@ -89,6 +155,19 @@ enum ice_adminq_opc { 
	/* AQ commands */

	/* AQ commands */

	ice_aqc_opc_get_ver				= 0x0001,

	ice_aqc_opc_get_ver				= 0x0001,

	ice_aqc_opc_q_shutdown				= 0x0003,

	ice_aqc_opc_q_shutdown				= 0x0003,



	/* resource ownership */

	ice_aqc_opc_req_res				= 0x0008,

	ice_aqc_opc_release_res				= 0x0009,



	/* PXE */

	ice_aqc_opc_clear_pxe_mode			= 0x0110,



	ice_aqc_opc_clear_pf_cfg			= 0x02A4,



	/* NVM commands */

	ice_aqc_opc_nvm_read				= 0x0701,



};

};





#endif /* _ICE_ADMINQ_CMD_H_ */
 
#endif /* _ICE_ADMINQ_CMD_H_ */

drivers/net/ethernet/intel/ice/ice_common.c

+405 −0
Original line number Original line Diff line number Diff line
@@ -4,6 +4,224 @@ 
#include "ice_common.h"

#include "ice_common.h"

#include "ice_adminq_cmd.h"

#include "ice_adminq_cmd.h"





#define ICE_PF_RESET_WAIT_COUNT	200



/**

 * ice_set_mac_type - Sets MAC type

 * @hw: pointer to the HW structure

 *

 * This function sets the MAC type of the adapter based on the

 * vendor ID and device ID stored in the hw structure.

 */

static enum ice_status ice_set_mac_type(struct ice_hw *hw)

{

	if (hw->vendor_id != PCI_VENDOR_ID_INTEL)

		return ICE_ERR_DEVICE_NOT_SUPPORTED;



	hw->mac_type = ICE_MAC_GENERIC;

	return 0;

}



/**

 * ice_clear_pf_cfg - Clear PF configuration

 * @hw: pointer to the hardware structure

 */

enum ice_status ice_clear_pf_cfg(struct ice_hw *hw)

{

	struct ice_aq_desc desc;



	ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pf_cfg);



	return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);

}



/**

 * ice_init_hw - main hardware initialization routine

 * @hw: pointer to the hardware structure

 */

enum ice_status ice_init_hw(struct ice_hw *hw)

{

	enum ice_status status;



	/* Set MAC type based on DeviceID */

	status = ice_set_mac_type(hw);

	if (status)

		return status;



	hw->pf_id = (u8)(rd32(hw, PF_FUNC_RID) &

			 PF_FUNC_RID_FUNC_NUM_M) >>

		PF_FUNC_RID_FUNC_NUM_S;



	status = ice_reset(hw, ICE_RESET_PFR);

	if (status)

		return status;



	status = ice_init_all_ctrlq(hw);

	if (status)

		goto err_unroll_cqinit;



	status = ice_clear_pf_cfg(hw);

	if (status)

		goto err_unroll_cqinit;



	ice_clear_pxe_mode(hw);



	status = ice_init_nvm(hw);

	if (status)

		goto err_unroll_cqinit;



	return 0;



err_unroll_cqinit:

	ice_shutdown_all_ctrlq(hw);

	return status;

}



/**

 * ice_deinit_hw - unroll initialization operations done by ice_init_hw

 * @hw: pointer to the hardware structure

 */

void ice_deinit_hw(struct ice_hw *hw)

{

	ice_shutdown_all_ctrlq(hw);

}



/**

 * ice_check_reset - Check to see if a global reset is complete

 * @hw: pointer to the hardware structure

 */

enum ice_status ice_check_reset(struct ice_hw *hw)

{

	u32 cnt, reg = 0, grst_delay;



	/* Poll for Device Active state in case a recent CORER, GLOBR,

	 * or EMPR has occurred. The grst delay value is in 100ms units.

	 * Add 1sec for outstanding AQ commands that can take a long time.

	 */

	grst_delay = ((rd32(hw, GLGEN_RSTCTL) & GLGEN_RSTCTL_GRSTDEL_M) >>

		      GLGEN_RSTCTL_GRSTDEL_S) + 10;



	for (cnt = 0; cnt < grst_delay; cnt++) {

		mdelay(100);

		reg = rd32(hw, GLGEN_RSTAT);

		if (!(reg & GLGEN_RSTAT_DEVSTATE_M))

			break;

	}



	if (cnt == grst_delay) {

		ice_debug(hw, ICE_DBG_INIT,

			  "Global reset polling failed to complete.\n");

		return ICE_ERR_RESET_FAILED;

	}



#define ICE_RESET_DONE_MASK	(GLNVM_ULD_CORER_DONE_M | \

				 GLNVM_ULD_GLOBR_DONE_M)



	/* Device is Active; check Global Reset processes are done */

	for (cnt = 0; cnt < ICE_PF_RESET_WAIT_COUNT; cnt++) {

		reg = rd32(hw, GLNVM_ULD) & ICE_RESET_DONE_MASK;

		if (reg == ICE_RESET_DONE_MASK) {

			ice_debug(hw, ICE_DBG_INIT,

				  "Global reset processes done. %d\n", cnt);

			break;

		}

		mdelay(10);

	}



	if (cnt == ICE_PF_RESET_WAIT_COUNT) {

		ice_debug(hw, ICE_DBG_INIT,

			  "Wait for Reset Done timed out. GLNVM_ULD = 0x%x\n",

			  reg);

		return ICE_ERR_RESET_FAILED;

	}



	return 0;

}



/**

 * ice_pf_reset - Reset the PF

 * @hw: pointer to the hardware structure

 *

 * If a global reset has been triggered, this function checks

 * for its completion and then issues the PF reset

 */

static enum ice_status ice_pf_reset(struct ice_hw *hw)

{

	u32 cnt, reg;



	/* If at function entry a global reset was already in progress, i.e.

	 * state is not 'device active' or any of the reset done bits are not

	 * set in GLNVM_ULD, there is no need for a PF Reset; poll until the

	 * global reset is done.

	 */

	if ((rd32(hw, GLGEN_RSTAT) & GLGEN_RSTAT_DEVSTATE_M) ||

	    (rd32(hw, GLNVM_ULD) & ICE_RESET_DONE_MASK) ^ ICE_RESET_DONE_MASK) {

		/* poll on global reset currently in progress until done */

		if (ice_check_reset(hw))

			return ICE_ERR_RESET_FAILED;



		return 0;

	}



	/* Reset the PF */

	reg = rd32(hw, PFGEN_CTRL);



	wr32(hw, PFGEN_CTRL, (reg | PFGEN_CTRL_PFSWR_M));



	for (cnt = 0; cnt < ICE_PF_RESET_WAIT_COUNT; cnt++) {

		reg = rd32(hw, PFGEN_CTRL);

		if (!(reg & PFGEN_CTRL_PFSWR_M))

			break;



		mdelay(1);

	}



	if (cnt == ICE_PF_RESET_WAIT_COUNT) {

		ice_debug(hw, ICE_DBG_INIT,

			  "PF reset polling failed to complete.\n");

		return ICE_ERR_RESET_FAILED;

	}



	return 0;

}



/**

 * ice_reset - Perform different types of reset

 * @hw: pointer to the hardware structure

 * @req: reset request

 *

 * This function triggers a reset as specified by the req parameter.

 *

 * Note:

 * If anything other than a PF reset is triggered, PXE mode is restored.

 * This has to be cleared using ice_clear_pxe_mode again, once the AQ

 * interface has been restored in the rebuild flow.

 */

enum ice_status ice_reset(struct ice_hw *hw, enum ice_reset_req req)

{

	u32 val = 0;



	switch (req) {

	case ICE_RESET_PFR:

		return ice_pf_reset(hw);

	case ICE_RESET_CORER:

		ice_debug(hw, ICE_DBG_INIT, "CoreR requested\n");

		val = GLGEN_RTRIG_CORER_M;

		break;

	case ICE_RESET_GLOBR:

		ice_debug(hw, ICE_DBG_INIT, "GlobalR requested\n");

		val = GLGEN_RTRIG_GLOBR_M;

		break;

	}



	val |= rd32(hw, GLGEN_RTRIG);

	wr32(hw, GLGEN_RTRIG, val);

	ice_flush(hw);



	/* wait for the FW to be ready */

	return ice_check_reset(hw);

}



/**

/**

 * ice_debug_cq

 * ice_debug_cq

 * @hw: pointer to the hardware structure

 * @hw: pointer to the hardware structure
@@ -128,3 +346,190 @@ enum ice_status ice_aq_q_shutdown(struct ice_hw *hw, bool unloading) 




	return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);

	return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);

}

}



/**

 * ice_aq_req_res

 * @hw: pointer to the hw struct

 * @res: resource id

 * @access: access type

 * @sdp_number: resource number

 * @timeout: the maximum time in ms that the driver may hold the resource

 * @cd: pointer to command details structure or NULL

 *

 * requests common resource using the admin queue commands (0x0008)

 */

static enum ice_status

ice_aq_req_res(struct ice_hw *hw, enum ice_aq_res_ids res,

	       enum ice_aq_res_access_type access, u8 sdp_number, u32 *timeout,

	       struct ice_sq_cd *cd)

{

	struct ice_aqc_req_res *cmd_resp;

	struct ice_aq_desc desc;

	enum ice_status status;



	cmd_resp = &desc.params.res_owner;



	ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_req_res);



	cmd_resp->res_id = cpu_to_le16(res);

	cmd_resp->access_type = cpu_to_le16(access);

	cmd_resp->res_number = cpu_to_le32(sdp_number);



	status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd);

	/* The completion specifies the maximum time in ms that the driver

	 * may hold the resource in the Timeout field.

	 * If the resource is held by someone else, the command completes with

	 * busy return value and the timeout field indicates the maximum time

	 * the current owner of the resource has to free it.

	 */

	if (!status || hw->adminq.sq_last_status == ICE_AQ_RC_EBUSY)

		*timeout = le32_to_cpu(cmd_resp->timeout);



	return status;

}



/**

 * ice_aq_release_res

 * @hw: pointer to the hw struct

 * @res: resource id

 * @sdp_number: resource number

 * @cd: pointer to command details structure or NULL

 *

 * release common resource using the admin queue commands (0x0009)

 */

static enum ice_status

ice_aq_release_res(struct ice_hw *hw, enum ice_aq_res_ids res, u8 sdp_number,

		   struct ice_sq_cd *cd)

{

	struct ice_aqc_req_res *cmd;

	struct ice_aq_desc desc;



	cmd = &desc.params.res_owner;



	ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_release_res);



	cmd->res_id = cpu_to_le16(res);

	cmd->res_number = cpu_to_le32(sdp_number);



	return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);

}



/**

 * ice_acquire_res

 * @hw: pointer to the HW structure

 * @res: resource id

 * @access: access type (read or write)

 *

 * This function will attempt to acquire the ownership of a resource.

 */

enum ice_status

ice_acquire_res(struct ice_hw *hw, enum ice_aq_res_ids res,

		enum ice_aq_res_access_type access)

{

#define ICE_RES_POLLING_DELAY_MS	10

	u32 delay = ICE_RES_POLLING_DELAY_MS;

	enum ice_status status;

	u32 time_left = 0;

	u32 timeout;



	status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL);



	/* An admin queue return code of ICE_AQ_RC_EEXIST means that another

	 * driver has previously acquired the resource and performed any

	 * necessary updates; in this case the caller does not obtain the

	 * resource and has no further work to do.

	 */

	if (hw->adminq.sq_last_status == ICE_AQ_RC_EEXIST) {

		status = ICE_ERR_AQ_NO_WORK;

		goto ice_acquire_res_exit;

	}



	if (status)

		ice_debug(hw, ICE_DBG_RES,

			  "resource %d acquire type %d failed.\n", res, access);



	/* If necessary, poll until the current lock owner timeouts */

	timeout = time_left;

	while (status && timeout && time_left) {

		mdelay(delay);

		timeout = (timeout > delay) ? timeout - delay : 0;

		status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL);



		if (hw->adminq.sq_last_status == ICE_AQ_RC_EEXIST) {

			/* lock free, but no work to do */

			status = ICE_ERR_AQ_NO_WORK;

			break;

		}



		if (!status)

			/* lock acquired */

			break;

	}

	if (status && status != ICE_ERR_AQ_NO_WORK)

		ice_debug(hw, ICE_DBG_RES, "resource acquire timed out.\n");



ice_acquire_res_exit:

	if (status == ICE_ERR_AQ_NO_WORK) {

		if (access == ICE_RES_WRITE)

			ice_debug(hw, ICE_DBG_RES,

				  "resource indicates no work to do.\n");

		else

			ice_debug(hw, ICE_DBG_RES,

				  "Warning: ICE_ERR_AQ_NO_WORK not expected\n");

	}

	return status;

}



/**

 * ice_release_res

 * @hw: pointer to the HW structure

 * @res: resource id

 *

 * This function will release a resource using the proper Admin Command.

 */

void ice_release_res(struct ice_hw *hw, enum ice_aq_res_ids res)

{

	enum ice_status status;

	u32 total_delay = 0;



	status = ice_aq_release_res(hw, res, 0, NULL);



	/* there are some rare cases when trying to release the resource

	 * results in an admin Q timeout, so handle them correctly

	 */

	while ((status == ICE_ERR_AQ_TIMEOUT) &&

	       (total_delay < hw->adminq.sq_cmd_timeout)) {

		mdelay(1);

		status = ice_aq_release_res(hw, res, 0, NULL);

		total_delay++;

	}

}



/**

 * ice_aq_clear_pxe_mode

 * @hw: pointer to the hw struct

 *

 * Tell the firmware that the driver is taking over from PXE (0x0110).

 */

static enum ice_status ice_aq_clear_pxe_mode(struct ice_hw *hw)

{

	struct ice_aq_desc desc;



	ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pxe_mode);

	desc.params.clear_pxe.rx_cnt = ICE_AQC_CLEAR_PXE_RX_CNT;



	return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);

}



/**

 * ice_clear_pxe_mode - clear pxe operations mode

 * @hw: pointer to the hw struct

 *

 * Make sure all PXE mode settings are cleared, including things

 * like descriptor fetch/write-back mode.

 */

void ice_clear_pxe_mode(struct ice_hw *hw)

{

	if (ice_check_sq_alive(hw, &hw->adminq))

		ice_aq_clear_pxe_mode(hw);

}

drivers/net/ethernet/intel/ice/ice_common.h

+11 −0
Original line number Original line Diff line number Diff line
@@ -9,12 +9,22 @@ 




void ice_debug_cq(struct ice_hw *hw, u32 mask, void *desc, void *buf,

void ice_debug_cq(struct ice_hw *hw, u32 mask, void *desc, void *buf,

		  u16 buf_len);

		  u16 buf_len);

enum ice_status ice_init_hw(struct ice_hw *hw);

void ice_deinit_hw(struct ice_hw *hw);

enum ice_status ice_check_reset(struct ice_hw *hw);

enum ice_status ice_reset(struct ice_hw *hw, enum ice_reset_req req);

enum ice_status ice_init_all_ctrlq(struct ice_hw *hw);

enum ice_status ice_init_all_ctrlq(struct ice_hw *hw);

void ice_shutdown_all_ctrlq(struct ice_hw *hw);

void ice_shutdown_all_ctrlq(struct ice_hw *hw);

enum ice_status

enum ice_status

ice_acquire_res(struct ice_hw *hw, enum ice_aq_res_ids res,

		enum ice_aq_res_access_type access);

void ice_release_res(struct ice_hw *hw, enum ice_aq_res_ids res);

enum ice_status ice_init_nvm(struct ice_hw *hw);

enum ice_status

ice_sq_send_cmd(struct ice_hw *hw, struct ice_ctl_q_info *cq,

ice_sq_send_cmd(struct ice_hw *hw, struct ice_ctl_q_info *cq,

		struct ice_aq_desc *desc, void *buf, u16 buf_size,

		struct ice_aq_desc *desc, void *buf, u16 buf_size,

		struct ice_sq_cd *cd);

		struct ice_sq_cd *cd);

void ice_clear_pxe_mode(struct ice_hw *hw);

bool ice_check_sq_alive(struct ice_hw *hw, struct ice_ctl_q_info *cq);

bool ice_check_sq_alive(struct ice_hw *hw, struct ice_ctl_q_info *cq);

enum ice_status ice_aq_q_shutdown(struct ice_hw *hw, bool unloading);

enum ice_status ice_aq_q_shutdown(struct ice_hw *hw, bool unloading);

void ice_fill_dflt_direct_cmd_desc(struct ice_aq_desc *desc, u16 opcode);

void ice_fill_dflt_direct_cmd_desc(struct ice_aq_desc *desc, u16 opcode);
@@ -22,4 +32,5 @@ enum ice_status 
ice_aq_send_cmd(struct ice_hw *hw, struct ice_aq_desc *desc,

ice_aq_send_cmd(struct ice_hw *hw, struct ice_aq_desc *desc,

		void *buf, u16 buf_size, struct ice_sq_cd *cd);

		void *buf, u16 buf_size, struct ice_sq_cd *cd);

enum ice_status ice_aq_get_fw_ver(struct ice_hw *hw, struct ice_sq_cd *cd);

enum ice_status ice_aq_get_fw_ver(struct ice_hw *hw, struct ice_sq_cd *cd);

enum ice_status ice_clear_pf_cfg(struct ice_hw *hw);

#endif /* _ICE_COMMON_H_ */
 
#endif /* _ICE_COMMON_H_ */