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Commit ee947859 authored by Mitko Haralanov's avatar Mitko Haralanov Committed by Greg Kroah-Hartman
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staging/rdma/hfi1: Allow tuning of SDMA interrupt rate 



The SDMA engines were configured to generate progress interrupts every time they
processed N/2 descriptors (where N is the size of the descriptor queue). This
interval was too infrequent, leading to degraded performance.

This commit adds a module parameter, as well as a recommended default, which
allows for the tuning of the interrupt frequency.

Reviewed-by: default avatarMike Marciniszyn <mike.marciniszyn@intel.com>
Signed-off-by: default avatarMitko Haralanov <mitko.haralanov@intel.com>
Signed-off-by: default avatarIra Weiny <ira.weiny@intel.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 3c6c065a

drivers/staging/rdma/hfi1/sdma.c

+9 −1
Original line number Original line Diff line number Diff line
@@ -66,6 +66,7 @@ 




/* must be a power of 2 >= 64 <= 32768 */

/* must be a power of 2 >= 64 <= 32768 */

#define SDMA_DESCQ_CNT 1024

#define SDMA_DESCQ_CNT 1024

#define SDMA_DESC_INTR 64

#define INVALID_TAIL 0xffff

#define INVALID_TAIL 0xffff





static uint sdma_descq_cnt = SDMA_DESCQ_CNT;

static uint sdma_descq_cnt = SDMA_DESCQ_CNT;
@@ -80,6 +81,10 @@ uint mod_num_sdma; 
module_param_named(num_sdma, mod_num_sdma, uint, S_IRUGO);

module_param_named(num_sdma, mod_num_sdma, uint, S_IRUGO);

MODULE_PARM_DESC(num_sdma, "Set max number SDMA engines to use");

MODULE_PARM_DESC(num_sdma, "Set max number SDMA engines to use");





static uint sdma_desct_intr = SDMA_DESC_INTR;

module_param_named(desct_intr, sdma_desct_intr, uint, S_IRUGO | S_IWUSR);

MODULE_PARM_DESC(desct_intr, "Number of SDMA descriptor before interrupt");



#define SDMA_WAIT_BATCH_SIZE 20

#define SDMA_WAIT_BATCH_SIZE 20

/* max wait time for a SDMA engine to indicate it has halted */

/* max wait time for a SDMA engine to indicate it has halted */

#define SDMA_ERR_HALT_TIMEOUT 10 /* ms */

#define SDMA_ERR_HALT_TIMEOUT 10 /* ms */
@@ -1046,6 +1051,9 @@ int sdma_init(struct hfi1_devdata *dd, u8 port) 
		return -ENOMEM;

		return -ENOMEM;





	idle_cnt = ns_to_cclock(dd, idle_cnt);

	idle_cnt = ns_to_cclock(dd, idle_cnt);

	if (!sdma_desct_intr)

		sdma_desct_intr = SDMA_DESC_INTR;



	/* Allocate memory for SendDMA descriptor FIFOs */

	/* Allocate memory for SendDMA descriptor FIFOs */

	for (this_idx = 0; this_idx < num_engines; ++this_idx) {

	for (this_idx = 0; this_idx < num_engines; ++this_idx) {

		sde = &dd->per_sdma[this_idx];

		sde = &dd->per_sdma[this_idx];
@@ -1546,7 +1554,7 @@ void sdma_engine_interrupt(struct sdma_engine *sde, u64 status) 
{

{

	trace_hfi1_sdma_engine_interrupt(sde, status);

	trace_hfi1_sdma_engine_interrupt(sde, status);

	write_seqlock(&sde->head_lock);

	write_seqlock(&sde->head_lock);

	sdma_set_desc_cnt(sde, sde->descq_cnt / 2);

	sdma_set_desc_cnt(sde, sdma_desct_intr);

	sdma_make_progress(sde, status);

	sdma_make_progress(sde, status);

	write_sequnlock(&sde->head_lock);

	write_sequnlock(&sde->head_lock);

}

}