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Commit ee39a3e3 authored by Chen-Yu Tsai's avatar Chen-Yu Tsai Committed by Maxime Ripard
Browse files

ARM: dts: sun6i: Add pin muxing options for GMAC 



The A31 SoC has a GMAC gigabit ethernet controller supporting
MII, GMII, RGMII modes. Add pin muxing options for these modes.

Signed-off-by: default avatarChen-Yu Tsai <wens@csie.org>
Signed-off-by: default avatarMaxime Ripard <maxime.ripard@free-electrons.com>
parent df02dd82

arch/arm/boot/dts/sun6i-a31.dtsi

+42 −0
Original line number Original line Diff line number Diff line
@@ -467,6 +467,48 @@ 
				allwinner,drive = <2>;

				allwinner,drive = <2>;

				allwinner,pull = <0>;

				allwinner,pull = <0>;

			};

			};



			gmac_pins_mii_a: gmac_mii@0 {

				allwinner,pins = "PA0", "PA1", "PA2", "PA3",

						"PA8", "PA9", "PA11",

						"PA12", "PA13", "PA14", "PA19",

						"PA20", "PA21", "PA22", "PA23",

						"PA24", "PA26", "PA27";

				allwinner,function = "gmac";

				allwinner,drive = <0>;

				allwinner,pull = <0>;

			};



			gmac_pins_gmii_a: gmac_gmii@0 {

				allwinner,pins = "PA0", "PA1", "PA2", "PA3",

						"PA4", "PA5", "PA6", "PA7",

						"PA8", "PA9", "PA10", "PA11",

						"PA12", "PA13", "PA14",	"PA15",

						"PA16", "PA17", "PA18", "PA19",

						"PA20", "PA21", "PA22", "PA23",

						"PA24", "PA25", "PA26", "PA27";

				allwinner,function = "gmac";

				/*

				 * data lines in GMII mode run at 125MHz and

				 * might need a higher signal drive strength

				 */

				allwinner,drive = <2>;

				allwinner,pull = <0>;

			};



			gmac_pins_rgmii_a: gmac_rgmii@0 {

				allwinner,pins = "PA0", "PA1", "PA2", "PA3",

						"PA9", "PA10", "PA11",

						"PA12", "PA13", "PA14", "PA19",

						"PA20", "PA25", "PA26", "PA27";

				allwinner,function = "gmac";

				/*

				 * data lines in RGMII mode use DDR mode

				 * and need a higher signal drive strength

				 */

				allwinner,drive = <3>;

				allwinner,pull = <0>;

			};

		};

		};





		ahb1_rst: reset@01c202c0 {

		ahb1_rst: reset@01c202c0 {