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Commit ecc124b0 authored by Rex Zhu's avatar Rex Zhu Committed by Alex Deucher
Browse files

drm/amd/pp: Delete the wrapper layer of smu_allocate/free_memory 



use amdgpu_bo_create/free_kernel instand.

Reviewed-by: default avatarAlex Deucher <alexdeucher@amd.com>
Acked-by: default avatarChristian König <christian.koenig@amd.com>
Signed-off-by: default avatarRex Zhu <Rex.Zhu@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 807f93ac

drivers/gpu/drm/amd/powerplay/inc/smumgr.h

+0 −7
Original line number Diff line number Diff line
@@ -106,13 +106,6 @@ extern int smum_send_msg_to_smc(struct pp_hwmgr *hwmgr, uint16_t msg); 
extern int smum_send_msg_to_smc_with_parameter(struct pp_hwmgr *hwmgr,

					uint16_t msg, uint32_t parameter);



extern int smu_allocate_memory(void *device, uint32_t size,

			 enum cgs_gpu_mem_type type,

			 uint32_t byte_align, uint64_t *mc_addr,

			 void **kptr, void *handle);



extern int smu_free_memory(void *device, void *handle);



extern int smum_update_sclk_threshold(struct pp_hwmgr *hwmgr);



extern int smum_update_smc_table(struct pp_hwmgr *hwmgr, uint32_t type);

drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c

+36 −48
Original line number Diff line number Diff line
@@ -347,8 +347,8 @@ static int cz_smu_populate_single_scratch_task( 
		return -EINVAL;

	}



	task->addr.low = cz_smu->scratch_buffer[i].mc_addr_low;

	task->addr.high = cz_smu->scratch_buffer[i].mc_addr_high;

	task->addr.low = smu_lower_32_bits(cz_smu->scratch_buffer[i].mc_addr);

	task->addr.high = smu_upper_32_bits(cz_smu->scratch_buffer[i].mc_addr);

	task->size_bytes = cz_smu->scratch_buffer[i].data_size;



	if (CZ_SCRATCH_ENTRY_DATA_ID_IH_REGISTERS == fw_enum) {
@@ -384,8 +384,8 @@ static int cz_smu_populate_single_ucode_load_task( 
		return -EINVAL;

	}



	task->addr.low = cz_smu->driver_buffer[i].mc_addr_low;

	task->addr.high = cz_smu->driver_buffer[i].mc_addr_high;

	task->addr.low = smu_lower_32_bits(cz_smu->driver_buffer[i].mc_addr);

	task->addr.high = smu_upper_32_bits(cz_smu->driver_buffer[i].mc_addr);

	task->size_bytes = cz_smu->driver_buffer[i].data_size;



	return 0;
@@ -566,11 +566,7 @@ static int cz_smu_populate_firmware_entries(struct pp_hwmgr *hwmgr) 
							ucode_id, &info);



		if (ret == 0) {

			cz_smu->driver_buffer[i].mc_addr_high =

					smu_upper_32_bits(info.mc_addr);



			cz_smu->driver_buffer[i].mc_addr_low =

					smu_lower_32_bits(info.mc_addr);

			cz_smu->driver_buffer[i].mc_addr = info.mc_addr;



			cz_smu->driver_buffer[i].data_size = info.image_size;
@@ -589,19 +585,12 @@ static int cz_smu_populate_single_scratch_entry( 
				struct cz_buffer_entry *entry)

{

	struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smu_backend;

	long long mc_addr =

			((long long)(cz_smu->smu_buffer.mc_addr_high) << 32)

			| cz_smu->smu_buffer.mc_addr_low;



	uint32_t ulsize_aligned = SIZE_ALIGN_32(ulsize_byte);



	mc_addr += cz_smu->smu_buffer_used_bytes;



	entry->data_size = ulsize_byte;

	entry->kaddr = (char *) cz_smu->smu_buffer.kaddr +

				cz_smu->smu_buffer_used_bytes;

	entry->mc_addr_low = smu_lower_32_bits(mc_addr);

	entry->mc_addr_high = smu_upper_32_bits(mc_addr);

	entry->mc_addr = cz_smu->smu_buffer.mc_addr + cz_smu->smu_buffer_used_bytes;

	entry->firmware_ID = scratch_type;



	cz_smu->smu_buffer_used_bytes += ulsize_aligned;
@@ -624,11 +613,11 @@ static int cz_download_pptable_settings(struct pp_hwmgr *hwmgr, void **table) 


	cz_send_msg_to_smc_with_parameter(hwmgr,

				PPSMC_MSG_SetClkTableAddrHi,

				cz_smu->scratch_buffer[i].mc_addr_high);

				smu_upper_32_bits(cz_smu->scratch_buffer[i].mc_addr));



	cz_send_msg_to_smc_with_parameter(hwmgr,

				PPSMC_MSG_SetClkTableAddrLo,

				cz_smu->scratch_buffer[i].mc_addr_low);

				smu_lower_32_bits(cz_smu->scratch_buffer[i].mc_addr));



	cz_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_ExecuteJob,

				cz_smu->toc_entry_clock_table);
@@ -651,11 +640,11 @@ static int cz_upload_pptable_settings(struct pp_hwmgr *hwmgr) 


	cz_send_msg_to_smc_with_parameter(hwmgr,

				PPSMC_MSG_SetClkTableAddrHi,

				cz_smu->scratch_buffer[i].mc_addr_high);

				smu_upper_32_bits(cz_smu->scratch_buffer[i].mc_addr));



	cz_send_msg_to_smc_with_parameter(hwmgr,

				PPSMC_MSG_SetClkTableAddrLo,

				cz_smu->scratch_buffer[i].mc_addr_low);

				smu_lower_32_bits(cz_smu->scratch_buffer[i].mc_addr));



	cz_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_ExecuteJob,

				cz_smu->toc_entry_clock_table);
@@ -686,11 +675,11 @@ static int cz_request_smu_load_fw(struct pp_hwmgr *hwmgr) 


	cz_send_msg_to_smc_with_parameter(hwmgr,

					PPSMC_MSG_DriverDramAddrHi,

					cz_smu->toc_buffer.mc_addr_high);

					smu_upper_32_bits(cz_smu->toc_buffer.mc_addr));



	cz_send_msg_to_smc_with_parameter(hwmgr,

					PPSMC_MSG_DriverDramAddrLo,

					cz_smu->toc_buffer.mc_addr_low);

					smu_lower_32_bits(cz_smu->toc_buffer.mc_addr));



	cz_send_msg_to_smc(hwmgr, PPSMC_MSG_InitJobs);
@@ -750,7 +739,6 @@ static int cz_start_smu(struct pp_hwmgr *hwmgr) 


static int cz_smu_init(struct pp_hwmgr *hwmgr)

{

	uint64_t mc_addr = 0;

	int ret = 0;

	struct cz_smumgr *cz_smu;
@@ -768,31 +756,29 @@ static int cz_smu_init(struct pp_hwmgr *hwmgr) 
		ALIGN(sizeof(struct SMU8_MultimediaPowerLogData), 32) +

		ALIGN(sizeof(struct SMU8_Fusion_ClkTable), 32);



	ret = smu_allocate_memory(hwmgr->device,

	ret = amdgpu_bo_create_kernel((struct amdgpu_device *)hwmgr->adev,

				cz_smu->toc_buffer.data_size,

				CGS_GPU_MEM_TYPE__GART_CACHEABLE,

				PAGE_SIZE,

				&mc_addr,

				&cz_smu->toc_buffer.kaddr,

				&cz_smu->toc_buffer.handle);

	if (ret != 0)

		return -1;



	cz_smu->toc_buffer.mc_addr_high = smu_upper_32_bits(mc_addr);

	cz_smu->toc_buffer.mc_addr_low = smu_lower_32_bits(mc_addr);

				AMDGPU_GEM_DOMAIN_VRAM,

				&cz_smu->toc_buffer.handle,

				&cz_smu->toc_buffer.mc_addr,

				&cz_smu->toc_buffer.kaddr);

	if (ret)

		return -EINVAL;



	ret = smu_allocate_memory(hwmgr->device,

	ret = amdgpu_bo_create_kernel((struct amdgpu_device *)hwmgr->adev,

				cz_smu->smu_buffer.data_size,

				CGS_GPU_MEM_TYPE__GART_CACHEABLE,

				PAGE_SIZE,

				&mc_addr,

				&cz_smu->smu_buffer.kaddr,

				&cz_smu->smu_buffer.handle);

	if (ret != 0)

		return -1;



	cz_smu->smu_buffer.mc_addr_high = smu_upper_32_bits(mc_addr);

	cz_smu->smu_buffer.mc_addr_low = smu_lower_32_bits(mc_addr);

				AMDGPU_GEM_DOMAIN_VRAM,

				&cz_smu->smu_buffer.handle,

				&cz_smu->smu_buffer.mc_addr,

				&cz_smu->smu_buffer.kaddr);

	if (ret) {

		amdgpu_bo_free_kernel(&cz_smu->toc_buffer.handle,

					&cz_smu->toc_buffer.mc_addr,

					&cz_smu->toc_buffer.kaddr);

		return -EINVAL;

	}



	if (0 != cz_smu_populate_single_scratch_entry(hwmgr,

		CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SCRATCH,
@@ -845,10 +831,12 @@ static int cz_smu_fini(struct pp_hwmgr *hwmgr) 


	cz_smu = (struct cz_smumgr *)hwmgr->smu_backend;

	if (cz_smu) {

		cgs_free_gpu_mem(hwmgr->device,

				cz_smu->toc_buffer.handle);

		cgs_free_gpu_mem(hwmgr->device,

				cz_smu->smu_buffer.handle);

		amdgpu_bo_free_kernel(&cz_smu->toc_buffer.handle,

					&cz_smu->toc_buffer.mc_addr,

					&cz_smu->toc_buffer.kaddr);

		amdgpu_bo_free_kernel(&cz_smu->smu_buffer.handle,

					&cz_smu->smu_buffer.mc_addr,

					&cz_smu->smu_buffer.kaddr);

		kfree(cz_smu);

	}

drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.h

+2 −3
Original line number Diff line number Diff line
@@ -60,11 +60,10 @@ enum cz_scratch_entry { 


struct cz_buffer_entry {

	uint32_t data_size;

	uint32_t mc_addr_low;

	uint32_t mc_addr_high;

	uint64_t mc_addr;

	void *kaddr;

	enum cz_scratch_entry firmware_ID;

	unsigned long handle; /* as bo handle used when release bo */

	struct amdgpu_bo *handle; /* as bo handle used when release bo */

};



struct cz_register_index_data_pair {

drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.c

+32 −39
Original line number Diff line number Diff line
@@ -169,11 +169,11 @@ int rv_copy_table_from_smc(struct pp_hwmgr *hwmgr, 
			"Invalid SMU Table Length!", return -EINVAL;);

	PP_ASSERT_WITH_CODE(rv_send_msg_to_smc_with_parameter(hwmgr,

			PPSMC_MSG_SetDriverDramAddrHigh,

			priv->smu_tables.entry[table_id].table_addr_high) == 0,

			smu_upper_32_bits(priv->smu_tables.entry[table_id].mc_addr)) == 0,

			"[CopyTableFromSMC] Attempt to Set Dram Addr High Failed!", return -EINVAL;);

	PP_ASSERT_WITH_CODE(rv_send_msg_to_smc_with_parameter(hwmgr,

			PPSMC_MSG_SetDriverDramAddrLow,

			priv->smu_tables.entry[table_id].table_addr_low) == 0,

			smu_lower_32_bits(priv->smu_tables.entry[table_id].mc_addr)) == 0,

			"[CopyTableFromSMC] Attempt to Set Dram Addr Low Failed!",

			return -EINVAL;);

	PP_ASSERT_WITH_CODE(rv_send_msg_to_smc_with_parameter(hwmgr,
@@ -182,7 +182,7 @@ int rv_copy_table_from_smc(struct pp_hwmgr *hwmgr, 
			"[CopyTableFromSMC] Attempt to Transfer Table From SMU Failed!",

			return -EINVAL;);



	memcpy(table, priv->smu_tables.entry[table_id].table,

	memcpy(table, (uint8_t *)priv->smu_tables.entry[table_id].table,

			priv->smu_tables.entry[table_id].size);



	return 0;
@@ -206,12 +206,12 @@ int rv_copy_table_to_smc(struct pp_hwmgr *hwmgr, 


	PP_ASSERT_WITH_CODE(rv_send_msg_to_smc_with_parameter(hwmgr,

			PPSMC_MSG_SetDriverDramAddrHigh,

			priv->smu_tables.entry[table_id].table_addr_high) == 0,

			smu_upper_32_bits(priv->smu_tables.entry[table_id].mc_addr)) == 0,

			"[CopyTableToSMC] Attempt to Set Dram Addr High Failed!",

			return -EINVAL;);

	PP_ASSERT_WITH_CODE(rv_send_msg_to_smc_with_parameter(hwmgr,

			PPSMC_MSG_SetDriverDramAddrLow,

			priv->smu_tables.entry[table_id].table_addr_low) == 0,

			smu_lower_32_bits(priv->smu_tables.entry[table_id].mc_addr)) == 0,

			"[CopyTableToSMC] Attempt to Set Dram Addr Low Failed!",

			return -EINVAL;);

	PP_ASSERT_WITH_CODE(rv_send_msg_to_smc_with_parameter(hwmgr,
@@ -292,10 +292,12 @@ static int rv_smu_fini(struct pp_hwmgr *hwmgr) 
	if (priv) {

		rv_smc_disable_sdma(hwmgr);

		rv_smc_disable_vcn(hwmgr);

		cgs_free_gpu_mem(hwmgr->device,

				priv->smu_tables.entry[WMTABLE].handle);

		cgs_free_gpu_mem(hwmgr->device,

				priv->smu_tables.entry[CLOCKTABLE].handle);

		amdgpu_bo_free_kernel(&priv->smu_tables.entry[WMTABLE].handle,

					&priv->smu_tables.entry[WMTABLE].mc_addr,

					priv->smu_tables.entry[WMTABLE].table);

		amdgpu_bo_free_kernel(&priv->smu_tables.entry[CLOCKTABLE].handle,

					&priv->smu_tables.entry[CLOCKTABLE].mc_addr,

					priv->smu_tables.entry[CLOCKTABLE].table);

		kfree(hwmgr->smu_backend);

		hwmgr->smu_backend = NULL;

	}
@@ -328,7 +330,8 @@ static int rv_smu_init(struct pp_hwmgr *hwmgr) 
	struct rv_smumgr *priv;

	uint64_t mc_addr;

	void *kaddr = NULL;

	unsigned long handle;

	struct amdgpu_bo *handle;

	int r;



	priv = kzalloc(sizeof(struct rv_smumgr), GFP_KERNEL);
@@ -338,54 +341,44 @@ static int rv_smu_init(struct pp_hwmgr *hwmgr) 
	hwmgr->smu_backend = priv;



	/* allocate space for watermarks table */

	smu_allocate_memory(hwmgr->device,

	r = amdgpu_bo_create_kernel((struct amdgpu_device *)hwmgr->adev,

			sizeof(Watermarks_t),

			CGS_GPU_MEM_TYPE__GART_CACHEABLE,

			PAGE_SIZE,

			AMDGPU_GEM_DOMAIN_VRAM,

			&handle,

			&mc_addr,

			&kaddr,

			&handle);

			&kaddr);



	PP_ASSERT_WITH_CODE(kaddr,

			"[rv_smu_init] Out of memory for wmtable.",

			kfree(hwmgr->smu_backend);

			hwmgr->smu_backend = NULL;

			return -EINVAL);

	if (r)

		return -EINVAL;



	priv->smu_tables.entry[WMTABLE].version = 0x01;

	priv->smu_tables.entry[WMTABLE].size = sizeof(Watermarks_t);

	priv->smu_tables.entry[WMTABLE].table_id = TABLE_WATERMARKS;

	priv->smu_tables.entry[WMTABLE].table_addr_high =

			smu_upper_32_bits(mc_addr);

	priv->smu_tables.entry[WMTABLE].table_addr_low =

			smu_lower_32_bits(mc_addr);

	priv->smu_tables.entry[WMTABLE].mc_addr = mc_addr;

	priv->smu_tables.entry[WMTABLE].table = kaddr;

	priv->smu_tables.entry[WMTABLE].handle = handle;



	/* allocate space for watermarks table */

	smu_allocate_memory(hwmgr->device,

	r = amdgpu_bo_create_kernel((struct amdgpu_device *)hwmgr->adev,

			sizeof(DpmClocks_t),

			CGS_GPU_MEM_TYPE__GART_CACHEABLE,

			PAGE_SIZE,

			AMDGPU_GEM_DOMAIN_VRAM,

			&handle,

			&mc_addr,

			&kaddr,

			&handle);

			&kaddr);



	PP_ASSERT_WITH_CODE(kaddr,

			"[rv_smu_init] Out of memory for CLOCKTABLE.",

			cgs_free_gpu_mem(hwmgr->device,

			(cgs_handle_t)priv->smu_tables.entry[WMTABLE].handle);

			kfree(hwmgr->smu_backend);

			hwmgr->smu_backend = NULL;

			return -EINVAL);

	if (r) {

		amdgpu_bo_free_kernel(&priv->smu_tables.entry[WMTABLE].handle,

					&priv->smu_tables.entry[WMTABLE].mc_addr,

					&priv->smu_tables.entry[WMTABLE].table);

		return -EINVAL;

	}



	priv->smu_tables.entry[CLOCKTABLE].version = 0x01;

	priv->smu_tables.entry[CLOCKTABLE].size = sizeof(DpmClocks_t);

	priv->smu_tables.entry[CLOCKTABLE].table_id = TABLE_DPMCLOCKS;

	priv->smu_tables.entry[CLOCKTABLE].table_addr_high =

			smu_upper_32_bits(mc_addr);

	priv->smu_tables.entry[CLOCKTABLE].table_addr_low =

			smu_lower_32_bits(mc_addr);

	priv->smu_tables.entry[CLOCKTABLE].mc_addr = mc_addr;

	priv->smu_tables.entry[CLOCKTABLE].table = kaddr;

	priv->smu_tables.entry[CLOCKTABLE].handle = handle;

drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.h

+3 −4
Original line number Diff line number Diff line
@@ -37,10 +37,9 @@ struct smu_table_entry { 
	uint32_t version;

	uint32_t size;

	uint32_t table_id;

	uint32_t table_addr_high;

	uint32_t table_addr_low;

	uint8_t *table;

	unsigned long handle;

	uint64_t mc_addr;

	void *table;

	struct amdgpu_bo *handle;

};



struct smu_table_array {