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Commit eafae133 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-msm-next-2017-06-20' of git://people.freedesktop.org/~robclark/linux into drm-next 

This time around, the biggest thing is a bunch of GEM rework for more
fine grained locking and prep work to handle multiple address spaces
(ie. per-process pagetables).  Also some HDMI fixes for 8x96
(snapdragon 820).

One unrelated bus patch, for something that seems to get merged
through whatever random tree (and has all the right ack's).

* tag 'drm-msm-next-2017-06-20' of git://people.freedesktop.org/~robclark/linux:
  drm/msm: Fix potential buffer overflow issue
  bus: SIMPLE_PM_BUS does not depend on ARCH_RENESAS
  drm/msm: Separate locking of buffer resources from struct_mutex
  drm/msm/hdmi: Fix HDMI pink strip issue seen on 8x96
  drm/msm/hdmi: 8996 PLL: Populate unprepare
  drm/msm/hdmi: Use bitwise operators when building register values
  drm/msm: update generated headers
  drm/msm: remove address-space id
  drm/msm: support for an arbitrary number of address spaces
  drm/msm: refactor how we handle vram carveout buffers
  drm/msm: pass address-space to _get_iova() and friends
  drm/msm/mdp4+5: move aspace/id to base class
  drm/msm/mdp5: kill pipe_lock
  drm/msm: fix locking inconsistency for gpu->hw_init()
  drm/msm: Remove memptrs->wptr
  drm/msm: Add a struct to pass configuration to msm_gpu_init()
  drm/msm: Add hint to DRM_IOCTL_MSM_GEM_INFO to return an object IOVA
  drm/msm: Remove idle function hook
  drm/msm: Remove DRM_MSM_NUM_IOCTLS
  drm/msm: gpu: Enable zap shader for A5XX
parents 8c52f364 4a630fad

drivers/bus/Kconfig

+0 −1
Original line number Original line Diff line number Diff line
@@ -121,7 +121,6 @@ config QCOM_EBI2 
config SIMPLE_PM_BUS

config SIMPLE_PM_BUS

	bool "Simple Power-Managed Bus Driver"

	bool "Simple Power-Managed Bus Driver"

	depends on OF && PM

	depends on OF && PM

	depends on ARCH_RENESAS || COMPILE_TEST

	help

	help

	  Driver for transparent busses that don't need a real driver, but

	  Driver for transparent busses that don't need a real driver, but

	  where the bus controller is part of a PM domain, or under the control

	  where the bus controller is part of a PM domain, or under the control

drivers/gpu/drm/msm/Kconfig

+1 −0
Original line number Original line Diff line number Diff line
@@ -5,6 +5,7 @@ config DRM_MSM 
	depends on ARCH_QCOM || (ARM && COMPILE_TEST)

	depends on ARCH_QCOM || (ARM && COMPILE_TEST)

	depends on OF && COMMON_CLK

	depends on OF && COMMON_CLK

	depends on MMU

	depends on MMU

	select QCOM_MDT_LOADER

	select REGULATOR

	select REGULATOR

	select DRM_KMS_HELPER

	select DRM_KMS_HELPER

	select DRM_PANEL

	select DRM_PANEL

drivers/gpu/drm/msm/adreno/a2xx.xml.h

+256 −11
Original line number Original line Diff line number Diff line
@@ -8,17 +8,17 @@ This file was generated by the rules-ng-ng headergen tool in this git repository 
git clone https://github.com/freedreno/envytools.git

git clone https://github.com/freedreno/envytools.git





The rules-ng-ng source files this header was generated from are:

The rules-ng-ng source files this header was generated from are:

- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml               (    431 bytes, from 2016-04-26 17:56:44)

- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml               (    431 bytes, from 2017-05-17 13:21:27)

- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml  (   1572 bytes, from 2016-02-10 17:07:21)

- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml  (   1572 bytes, from 2017-05-17 13:21:27)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml          (  32907 bytes, from 2016-11-26 23:01:08)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml          (  37162 bytes, from 2017-05-17 13:21:27)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml (  12025 bytes, from 2016-11-26 23:01:08)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml (  13324 bytes, from 2017-05-17 13:21:27)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml    (  22544 bytes, from 2016-11-26 23:01:08)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml    (  31866 bytes, from 2017-06-06 18:26:14)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml          (  83840 bytes, from 2016-11-26 23:01:08)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml          (  83840 bytes, from 2017-05-17 13:21:27)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml          ( 110765 bytes, from 2016-11-26 23:01:48)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml          ( 111898 bytes, from 2017-06-06 18:23:59)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml          (  90321 bytes, from 2016-11-28 16:50:05)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml          ( 139480 bytes, from 2017-06-16 12:44:39)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml         (   1773 bytes, from 2015-09-24 17:30:00)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml         (   1773 bytes, from 2017-05-17 13:21:27)





Copyright (C) 2013-2016 by the following authors:

Copyright (C) 2013-2017 by the following authors:

- Rob Clark <robdclark@gmail.com> (robclark)

- Rob Clark <robdclark@gmail.com> (robclark)

- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)

- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
@@ -352,6 +352,38 @@ static inline uint32_t A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR(enum adreno_mmu_cln 
#define REG_A2XX_RBBM_DEBUG					0x0000039b

#define REG_A2XX_RBBM_DEBUG					0x0000039b





#define REG_A2XX_RBBM_PM_OVERRIDE1				0x0000039c

#define REG_A2XX_RBBM_PM_OVERRIDE1				0x0000039c

#define A2XX_RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE		0x00000001

#define A2XX_RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE		0x00000002

#define A2XX_RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE		0x00000004

#define A2XX_RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE		0x00000008

#define A2XX_RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE		0x00000010

#define A2XX_RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE		0x00000020

#define A2XX_RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE	0x00000040

#define A2XX_RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE	0x00000080

#define A2XX_RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE		0x00000100

#define A2XX_RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE		0x00000200

#define A2XX_RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE		0x00000400

#define A2XX_RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE		0x00000800

#define A2XX_RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE		0x00001000

#define A2XX_RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE		0x00002000

#define A2XX_RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE		0x00004000

#define A2XX_RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE		0x00008000

#define A2XX_RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE		0x00010000

#define A2XX_RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE		0x00020000

#define A2XX_RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE		0x00040000

#define A2XX_RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE	0x00080000

#define A2XX_RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE		0x00100000

#define A2XX_RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE		0x00200000

#define A2XX_RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE		0x00400000

#define A2XX_RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE		0x00800000

#define A2XX_RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE	0x01000000

#define A2XX_RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE		0x02000000

#define A2XX_RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE		0x04000000

#define A2XX_RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE		0x08000000

#define A2XX_RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE		0x10000000

#define A2XX_RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE		0x20000000

#define A2XX_RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE		0x40000000

#define A2XX_RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE	0x80000000





#define REG_A2XX_RBBM_PM_OVERRIDE2				0x0000039d

#define REG_A2XX_RBBM_PM_OVERRIDE2				0x0000039d
@@ -477,12 +509,43 @@ static inline uint32_t REG_A2XX_VSC_PIPE_DATA_LENGTH(uint32_t i0) { return 0x000 
#define REG_A2XX_PA_SU_DEBUG_DATA				0x00000c81

#define REG_A2XX_PA_SU_DEBUG_DATA				0x00000c81





#define REG_A2XX_PA_SU_FACE_DATA				0x00000c86

#define REG_A2XX_PA_SU_FACE_DATA				0x00000c86

#define A2XX_PA_SU_FACE_DATA_BASE_ADDR__MASK			0xffffffe0

#define A2XX_PA_SU_FACE_DATA_BASE_ADDR__SHIFT			5

static inline uint32_t A2XX_PA_SU_FACE_DATA_BASE_ADDR(uint32_t val)

{

	return ((val) << A2XX_PA_SU_FACE_DATA_BASE_ADDR__SHIFT) & A2XX_PA_SU_FACE_DATA_BASE_ADDR__MASK;

}





#define REG_A2XX_SQ_GPR_MANAGEMENT				0x00000d00

#define REG_A2XX_SQ_GPR_MANAGEMENT				0x00000d00

#define A2XX_SQ_GPR_MANAGEMENT_REG_DYNAMIC			0x00000001

#define A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_PIX__MASK		0x00000ff0

#define A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_PIX__SHIFT		4

static inline uint32_t A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_PIX(uint32_t val)

{

	return ((val) << A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_PIX__SHIFT) & A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_PIX__MASK;

}

#define A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_VTX__MASK		0x000ff000

#define A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_VTX__SHIFT		12

static inline uint32_t A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_VTX(uint32_t val)

{

	return ((val) << A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_VTX__SHIFT) & A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_VTX__MASK;

}





#define REG_A2XX_SQ_FLOW_CONTROL				0x00000d01

#define REG_A2XX_SQ_FLOW_CONTROL				0x00000d01





#define REG_A2XX_SQ_INST_STORE_MANAGMENT			0x00000d02

#define REG_A2XX_SQ_INST_STORE_MANAGMENT			0x00000d02

#define A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_PIX__MASK	0x00000fff

#define A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_PIX__SHIFT	0

static inline uint32_t A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_PIX(uint32_t val)

{

	return ((val) << A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_PIX__SHIFT) & A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_PIX__MASK;

}

#define A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_VTX__MASK	0x0fff0000

#define A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_VTX__SHIFT	16

static inline uint32_t A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_VTX(uint32_t val)

{

	return ((val) << A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_VTX__SHIFT) & A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_VTX__MASK;

}





#define REG_A2XX_SQ_DEBUG_MISC					0x00000d05

#define REG_A2XX_SQ_DEBUG_MISC					0x00000d05
@@ -742,6 +805,24 @@ static inline uint32_t A2XX_PA_SC_WINDOW_SCISSOR_BR_Y(uint32_t val) 
#define REG_A2XX_RB_BLEND_ALPHA					0x00002108

#define REG_A2XX_RB_BLEND_ALPHA					0x00002108





#define REG_A2XX_RB_FOG_COLOR					0x00002109

#define REG_A2XX_RB_FOG_COLOR					0x00002109

#define A2XX_RB_FOG_COLOR_FOG_RED__MASK				0x000000ff

#define A2XX_RB_FOG_COLOR_FOG_RED__SHIFT			0

static inline uint32_t A2XX_RB_FOG_COLOR_FOG_RED(uint32_t val)

{

	return ((val) << A2XX_RB_FOG_COLOR_FOG_RED__SHIFT) & A2XX_RB_FOG_COLOR_FOG_RED__MASK;

}

#define A2XX_RB_FOG_COLOR_FOG_GREEN__MASK			0x0000ff00

#define A2XX_RB_FOG_COLOR_FOG_GREEN__SHIFT			8

static inline uint32_t A2XX_RB_FOG_COLOR_FOG_GREEN(uint32_t val)

{

	return ((val) << A2XX_RB_FOG_COLOR_FOG_GREEN__SHIFT) & A2XX_RB_FOG_COLOR_FOG_GREEN__MASK;

}

#define A2XX_RB_FOG_COLOR_FOG_BLUE__MASK			0x00ff0000

#define A2XX_RB_FOG_COLOR_FOG_BLUE__SHIFT			16

static inline uint32_t A2XX_RB_FOG_COLOR_FOG_BLUE(uint32_t val)

{

	return ((val) << A2XX_RB_FOG_COLOR_FOG_BLUE__SHIFT) & A2XX_RB_FOG_COLOR_FOG_BLUE__MASK;

}





#define REG_A2XX_RB_STENCILREFMASK_BF				0x0000210c

#define REG_A2XX_RB_STENCILREFMASK_BF				0x0000210c

#define A2XX_RB_STENCILREFMASK_BF_STENCILREF__MASK		0x000000ff

#define A2XX_RB_STENCILREFMASK_BF_STENCILREF__MASK		0x000000ff
@@ -890,14 +971,146 @@ static inline uint32_t A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS(uint32_t val) 
#define A2XX_SQ_CONTEXT_MISC_TX_CACHE_SEL			0x00040000

#define A2XX_SQ_CONTEXT_MISC_TX_CACHE_SEL			0x00040000





#define REG_A2XX_SQ_INTERPOLATOR_CNTL				0x00002182

#define REG_A2XX_SQ_INTERPOLATOR_CNTL				0x00002182

#define A2XX_SQ_INTERPOLATOR_CNTL_PARAM_SHADE__MASK		0x0000ffff

#define A2XX_SQ_INTERPOLATOR_CNTL_PARAM_SHADE__SHIFT		0

static inline uint32_t A2XX_SQ_INTERPOLATOR_CNTL_PARAM_SHADE(uint32_t val)

{

	return ((val) << A2XX_SQ_INTERPOLATOR_CNTL_PARAM_SHADE__SHIFT) & A2XX_SQ_INTERPOLATOR_CNTL_PARAM_SHADE__MASK;

}

#define A2XX_SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN__MASK	0xffff0000

#define A2XX_SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN__SHIFT	16

static inline uint32_t A2XX_SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN(uint32_t val)

{

	return ((val) << A2XX_SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN__SHIFT) & A2XX_SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN__MASK;

}





#define REG_A2XX_SQ_WRAPPING_0					0x00002183

#define REG_A2XX_SQ_WRAPPING_0					0x00002183

#define A2XX_SQ_WRAPPING_0_PARAM_WRAP_0__MASK			0x0000000f

#define A2XX_SQ_WRAPPING_0_PARAM_WRAP_0__SHIFT			0

static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_0(uint32_t val)

{

	return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_0__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_0__MASK;

}

#define A2XX_SQ_WRAPPING_0_PARAM_WRAP_1__MASK			0x000000f0

#define A2XX_SQ_WRAPPING_0_PARAM_WRAP_1__SHIFT			4

static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_1(uint32_t val)

{

	return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_1__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_1__MASK;

}

#define A2XX_SQ_WRAPPING_0_PARAM_WRAP_2__MASK			0x00000f00

#define A2XX_SQ_WRAPPING_0_PARAM_WRAP_2__SHIFT			8

static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_2(uint32_t val)

{

	return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_2__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_2__MASK;

}

#define A2XX_SQ_WRAPPING_0_PARAM_WRAP_3__MASK			0x0000f000

#define A2XX_SQ_WRAPPING_0_PARAM_WRAP_3__SHIFT			12

static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_3(uint32_t val)

{

	return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_3__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_3__MASK;

}

#define A2XX_SQ_WRAPPING_0_PARAM_WRAP_4__MASK			0x000f0000

#define A2XX_SQ_WRAPPING_0_PARAM_WRAP_4__SHIFT			16

static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_4(uint32_t val)

{

	return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_4__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_4__MASK;

}

#define A2XX_SQ_WRAPPING_0_PARAM_WRAP_5__MASK			0x00f00000

#define A2XX_SQ_WRAPPING_0_PARAM_WRAP_5__SHIFT			20

static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_5(uint32_t val)

{

	return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_5__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_5__MASK;

}

#define A2XX_SQ_WRAPPING_0_PARAM_WRAP_6__MASK			0x0f000000

#define A2XX_SQ_WRAPPING_0_PARAM_WRAP_6__SHIFT			24

static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_6(uint32_t val)

{

	return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_6__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_6__MASK;

}

#define A2XX_SQ_WRAPPING_0_PARAM_WRAP_7__MASK			0xf0000000

#define A2XX_SQ_WRAPPING_0_PARAM_WRAP_7__SHIFT			28

static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_7(uint32_t val)

{

	return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_7__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_7__MASK;

}





#define REG_A2XX_SQ_WRAPPING_1					0x00002184

#define REG_A2XX_SQ_WRAPPING_1					0x00002184

#define A2XX_SQ_WRAPPING_1_PARAM_WRAP_8__MASK			0x0000000f

#define A2XX_SQ_WRAPPING_1_PARAM_WRAP_8__SHIFT			0

static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_8(uint32_t val)

{

	return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_8__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_8__MASK;

}

#define A2XX_SQ_WRAPPING_1_PARAM_WRAP_9__MASK			0x000000f0

#define A2XX_SQ_WRAPPING_1_PARAM_WRAP_9__SHIFT			4

static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_9(uint32_t val)

{

	return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_9__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_9__MASK;

}

#define A2XX_SQ_WRAPPING_1_PARAM_WRAP_10__MASK			0x00000f00

#define A2XX_SQ_WRAPPING_1_PARAM_WRAP_10__SHIFT			8

static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_10(uint32_t val)

{

	return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_10__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_10__MASK;

}

#define A2XX_SQ_WRAPPING_1_PARAM_WRAP_11__MASK			0x0000f000

#define A2XX_SQ_WRAPPING_1_PARAM_WRAP_11__SHIFT			12

static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_11(uint32_t val)

{

	return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_11__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_11__MASK;

}

#define A2XX_SQ_WRAPPING_1_PARAM_WRAP_12__MASK			0x000f0000

#define A2XX_SQ_WRAPPING_1_PARAM_WRAP_12__SHIFT			16

static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_12(uint32_t val)

{

	return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_12__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_12__MASK;

}

#define A2XX_SQ_WRAPPING_1_PARAM_WRAP_13__MASK			0x00f00000

#define A2XX_SQ_WRAPPING_1_PARAM_WRAP_13__SHIFT			20

static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_13(uint32_t val)

{

	return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_13__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_13__MASK;

}

#define A2XX_SQ_WRAPPING_1_PARAM_WRAP_14__MASK			0x0f000000

#define A2XX_SQ_WRAPPING_1_PARAM_WRAP_14__SHIFT			24

static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_14(uint32_t val)

{

	return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_14__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_14__MASK;

}

#define A2XX_SQ_WRAPPING_1_PARAM_WRAP_15__MASK			0xf0000000

#define A2XX_SQ_WRAPPING_1_PARAM_WRAP_15__SHIFT			28

static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_15(uint32_t val)

{

	return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_15__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_15__MASK;

}





#define REG_A2XX_SQ_PS_PROGRAM					0x000021f6

#define REG_A2XX_SQ_PS_PROGRAM					0x000021f6

#define A2XX_SQ_PS_PROGRAM_BASE__MASK				0x00000fff

#define A2XX_SQ_PS_PROGRAM_BASE__SHIFT				0

static inline uint32_t A2XX_SQ_PS_PROGRAM_BASE(uint32_t val)

{

	return ((val) << A2XX_SQ_PS_PROGRAM_BASE__SHIFT) & A2XX_SQ_PS_PROGRAM_BASE__MASK;

}

#define A2XX_SQ_PS_PROGRAM_SIZE__MASK				0x00fff000

#define A2XX_SQ_PS_PROGRAM_SIZE__SHIFT				12

static inline uint32_t A2XX_SQ_PS_PROGRAM_SIZE(uint32_t val)

{

	return ((val) << A2XX_SQ_PS_PROGRAM_SIZE__SHIFT) & A2XX_SQ_PS_PROGRAM_SIZE__MASK;

}





#define REG_A2XX_SQ_VS_PROGRAM					0x000021f7

#define REG_A2XX_SQ_VS_PROGRAM					0x000021f7

#define A2XX_SQ_VS_PROGRAM_BASE__MASK				0x00000fff

#define A2XX_SQ_VS_PROGRAM_BASE__SHIFT				0

static inline uint32_t A2XX_SQ_VS_PROGRAM_BASE(uint32_t val)

{

	return ((val) << A2XX_SQ_VS_PROGRAM_BASE__SHIFT) & A2XX_SQ_VS_PROGRAM_BASE__MASK;

}

#define A2XX_SQ_VS_PROGRAM_SIZE__MASK				0x00fff000

#define A2XX_SQ_VS_PROGRAM_SIZE__SHIFT				12

static inline uint32_t A2XX_SQ_VS_PROGRAM_SIZE(uint32_t val)

{

	return ((val) << A2XX_SQ_VS_PROGRAM_SIZE__SHIFT) & A2XX_SQ_VS_PROGRAM_SIZE__MASK;

}





#define REG_A2XX_VGT_EVENT_INITIATOR				0x000021f9

#define REG_A2XX_VGT_EVENT_INITIATOR				0x000021f9
@@ -1304,6 +1517,14 @@ static inline uint32_t A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL(enum a2xx_pa_sc_a 
}

}





#define REG_A2XX_PA_SC_VIZ_QUERY				0x00002293

#define REG_A2XX_PA_SC_VIZ_QUERY				0x00002293

#define A2XX_PA_SC_VIZ_QUERY_VIZ_QUERY_ENA			0x00000001

#define A2XX_PA_SC_VIZ_QUERY_VIZ_QUERY_ID__MASK			0x0000007e

#define A2XX_PA_SC_VIZ_QUERY_VIZ_QUERY_ID__SHIFT		1

static inline uint32_t A2XX_PA_SC_VIZ_QUERY_VIZ_QUERY_ID(uint32_t val)

{

	return ((val) << A2XX_PA_SC_VIZ_QUERY_VIZ_QUERY_ID__SHIFT) & A2XX_PA_SC_VIZ_QUERY_VIZ_QUERY_ID__MASK;

}

#define A2XX_PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z		0x00000100





#define REG_A2XX_VGT_ENHANCE					0x00002294

#define REG_A2XX_VGT_ENHANCE					0x00002294
@@ -1319,6 +1540,18 @@ static inline uint32_t A2XX_PA_SC_LINE_CNTL_BRES_CNTL(uint32_t val) 
#define A2XX_PA_SC_LINE_CNTL_LAST_PIXEL				0x00000400

#define A2XX_PA_SC_LINE_CNTL_LAST_PIXEL				0x00000400





#define REG_A2XX_PA_SC_AA_CONFIG				0x00002301

#define REG_A2XX_PA_SC_AA_CONFIG				0x00002301

#define A2XX_PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES__MASK		0x00000007

#define A2XX_PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES__SHIFT		0

static inline uint32_t A2XX_PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES(uint32_t val)

{

	return ((val) << A2XX_PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES__SHIFT) & A2XX_PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES__MASK;

}

#define A2XX_PA_SC_AA_CONFIG_MAX_SAMPLE_DIST__MASK		0x0001e000

#define A2XX_PA_SC_AA_CONFIG_MAX_SAMPLE_DIST__SHIFT		13

static inline uint32_t A2XX_PA_SC_AA_CONFIG_MAX_SAMPLE_DIST(uint32_t val)

{

	return ((val) << A2XX_PA_SC_AA_CONFIG_MAX_SAMPLE_DIST__SHIFT) & A2XX_PA_SC_AA_CONFIG_MAX_SAMPLE_DIST__MASK;

}





#define REG_A2XX_PA_SU_VTX_CNTL					0x00002302

#define REG_A2XX_PA_SU_VTX_CNTL					0x00002302

#define A2XX_PA_SU_VTX_CNTL_PIX_CENTER__MASK			0x00000001

#define A2XX_PA_SU_VTX_CNTL_PIX_CENTER__MASK			0x00000001
@@ -1407,8 +1640,20 @@ static inline uint32_t A2XX_SQ_PS_CONST_SIZE(uint32_t val) 
#define REG_A2XX_PA_SC_AA_MASK					0x00002312

#define REG_A2XX_PA_SC_AA_MASK					0x00002312





#define REG_A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL			0x00002316

#define REG_A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL			0x00002316

#define A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH__MASK	0x00000007

#define A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH__SHIFT	0

static inline uint32_t A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH(uint32_t val)

{

	return ((val) << A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH__SHIFT) & A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH__MASK;

}





#define REG_A2XX_VGT_OUT_DEALLOC_CNTL				0x00002317

#define REG_A2XX_VGT_OUT_DEALLOC_CNTL				0x00002317

#define A2XX_VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST__MASK		0x00000003

#define A2XX_VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST__SHIFT		0

static inline uint32_t A2XX_VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST(uint32_t val)

{

	return ((val) << A2XX_VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST__SHIFT) & A2XX_VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST__MASK;

}





#define REG_A2XX_RB_COPY_CONTROL				0x00002318

#define REG_A2XX_RB_COPY_CONTROL				0x00002318

#define A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT__MASK		0x00000007

#define A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT__MASK		0x00000007

drivers/gpu/drm/msm/adreno/a3xx.xml.h

+11 −11
Original line number Original line Diff line number Diff line
@@ -8,17 +8,17 @@ This file was generated by the rules-ng-ng headergen tool in this git repository 
git clone https://github.com/freedreno/envytools.git

git clone https://github.com/freedreno/envytools.git





The rules-ng-ng source files this header was generated from are:

The rules-ng-ng source files this header was generated from are:

- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml               (    431 bytes, from 2016-04-26 17:56:44)

- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml               (    431 bytes, from 2017-05-17 13:21:27)

- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml  (   1572 bytes, from 2016-02-10 17:07:21)

- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml  (   1572 bytes, from 2017-05-17 13:21:27)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml          (  32907 bytes, from 2016-11-26 23:01:08)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml          (  37162 bytes, from 2017-05-17 13:21:27)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml (  12025 bytes, from 2016-11-26 23:01:08)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml (  13324 bytes, from 2017-05-17 13:21:27)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml    (  22544 bytes, from 2016-11-26 23:01:08)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml    (  31866 bytes, from 2017-06-06 18:26:14)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml          (  83840 bytes, from 2016-11-26 23:01:08)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml          (  83840 bytes, from 2017-05-17 13:21:27)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml          ( 110765 bytes, from 2016-11-26 23:01:48)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml          ( 111898 bytes, from 2017-06-06 18:23:59)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml          (  90321 bytes, from 2016-11-28 16:50:05)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml          ( 139480 bytes, from 2017-06-16 12:44:39)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml         (   1773 bytes, from 2015-09-24 17:30:00)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml         (   1773 bytes, from 2017-05-17 13:21:27)





Copyright (C) 2013-2016 by the following authors:

Copyright (C) 2013-2017 by the following authors:

- Rob Clark <robdclark@gmail.com> (robclark)

- Rob Clark <robdclark@gmail.com> (robclark)

- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)

- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)

drivers/gpu/drm/msm/adreno/a3xx_gpu.c

+2 −2
Original line number Original line Diff line number Diff line
@@ -40,6 +40,7 @@ 
extern bool hang_debug;

extern bool hang_debug;





static void a3xx_dump(struct msm_gpu *gpu);

static void a3xx_dump(struct msm_gpu *gpu);

static bool a3xx_idle(struct msm_gpu *gpu);





static bool a3xx_me_init(struct msm_gpu *gpu)

static bool a3xx_me_init(struct msm_gpu *gpu)

{

{
@@ -65,7 +66,7 @@ static bool a3xx_me_init(struct msm_gpu *gpu) 
	OUT_RING(ring, 0x00000000);

	OUT_RING(ring, 0x00000000);





	gpu->funcs->flush(gpu);

	gpu->funcs->flush(gpu);

	return gpu->funcs->idle(gpu);

	return a3xx_idle(gpu);

}

}





static int a3xx_hw_init(struct msm_gpu *gpu)

static int a3xx_hw_init(struct msm_gpu *gpu)
@@ -446,7 +447,6 @@ static const struct adreno_gpu_funcs funcs = { 
		.last_fence = adreno_last_fence,

		.last_fence = adreno_last_fence,

		.submit = adreno_submit,

		.submit = adreno_submit,

		.flush = adreno_flush,

		.flush = adreno_flush,

		.idle = a3xx_idle,

		.irq = a3xx_irq,

		.irq = a3xx_irq,

		.destroy = a3xx_destroy,

		.destroy = a3xx_destroy,

#ifdef CONFIG_DEBUG_FS

#ifdef CONFIG_DEBUG_FS