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Commit e5343503 authored by Suzuki K Poulose's avatar Suzuki K Poulose Committed by Catalin Marinas
Browse files

arm64: cpufeature: Correct feature register tables 



Correct the feature bit entries for :
  ID_DFR0
  ID_MMFR0

to fix the default safe value for some of the bits.

Signed-off-by: default avatarSuzuki K. Poulose <suzuki.poulose@arm.com>
Acked-by: default avatarWill Deacon <will.deacon@arm.com>
Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
parent 13f417f3

arch/arm64/kernel/cpufeature.c

+15 −3
Original line number Diff line number Diff line
@@ -150,12 +150,12 @@ static struct arm64_ftr_bits ftr_ctr[] = { 
};



static struct arm64_ftr_bits ftr_id_mmfr0[] = {

	ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 28, 4, 0),	/* InnerShr */

	ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 28, 4, 0xf),	/* InnerShr */

	ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 24, 4, 0),	/* FCSE */

	ARM64_FTR_BITS(FTR_NONSTRICT, FTR_LOWER_SAFE, 20, 4, 0),	/* AuxReg */

	ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 16, 4, 0),	/* TCM */

	ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 12, 4, 0),	/* ShareLvl */

	ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 8, 4, 0),	/* OuterShr */

	ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 8, 4, 0xf),	/* OuterShr */

	ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 4, 0),	/* PMSA */

	ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 4, 0),	/* VMSA */

	ARM64_FTR_END,
@@ -214,6 +214,18 @@ static struct arm64_ftr_bits ftr_id_pfr0[] = { 
	ARM64_FTR_END,

};



static struct arm64_ftr_bits ftr_id_dfr0[] = {

	ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0),

	ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0xf),	/* PerfMon */

	ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),

	ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),

	ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),

	ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),

	ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),

	ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),

	ARM64_FTR_END,

};



/*

 * Common ftr bits for a 32bit register with all hidden, strict

 * attributes, with 4bit feature fields and a default safe value of
@@ -259,7 +271,7 @@ static struct arm64_ftr_reg arm64_ftr_regs[] = { 
	/* Op1 = 0, CRn = 0, CRm = 1 */

	ARM64_FTR_REG(SYS_ID_PFR0_EL1, ftr_id_pfr0),

	ARM64_FTR_REG(SYS_ID_PFR1_EL1, ftr_generic_32bits),

	ARM64_FTR_REG(SYS_ID_DFR0_EL1, ftr_generic_32bits),

	ARM64_FTR_REG(SYS_ID_DFR0_EL1, ftr_id_dfr0),

	ARM64_FTR_REG(SYS_ID_MMFR0_EL1, ftr_id_mmfr0),

	ARM64_FTR_REG(SYS_ID_MMFR1_EL1, ftr_generic_32bits),

	ARM64_FTR_REG(SYS_ID_MMFR2_EL1, ftr_generic_32bits),