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Commit e3a6dadc authored by Tang Yuantian's avatar Tang Yuantian Committed by Tejun Heo
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ahci: qoriq: Update the default Rx watermark value 



The PTC[RXWM] sets the watermark value for Rx FIFO. The default
value 0x20 might be insufficient for some hard drives. If the
watermark value is too small, a single-cycle overflow may occur
and is reported as a CRC or internal error in the PxSERR register.
Updated the value to 0x29 according to the validation test.
All LS platforms are affected.

Signed-off-by: default avatarTang Yuantian <Yuantian.Tang@freescale.com>
Signed-off-by: default avatarTejun Heo <tj@kernel.org>
parent ef0cc7fe

drivers/ata/ahci_qoriq.c

+2 −1
Original line number Original line Diff line number Diff line
@@ -38,7 +38,7 @@ 
#define AHCI_PORT_PHY_3_CFG	0x0e081004

#define AHCI_PORT_PHY_3_CFG	0x0e081004

#define AHCI_PORT_PHY_4_CFG	0x00480811

#define AHCI_PORT_PHY_4_CFG	0x00480811

#define AHCI_PORT_PHY_5_CFG	0x192c96a4

#define AHCI_PORT_PHY_5_CFG	0x192c96a4

#define AHCI_PORT_TRANS_CFG	0x08000025

#define AHCI_PORT_TRANS_CFG	0x08000029

#define LS1043A_PORT_PHY2	0x28184d1f

#define LS1043A_PORT_PHY2	0x28184d1f

#define LS1043A_PORT_PHY3	0x0e081509

#define LS1043A_PORT_PHY3	0x0e081509
@@ -169,6 +169,7 @@ static int ahci_qoriq_phy_init(struct ahci_host_priv *hpriv) 




	case AHCI_LS2080A:

	case AHCI_LS2080A:

		writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);

		writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);

		writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);

		break;

		break;

	}

	}