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Commit df2e37c8 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 

Pull irq updates from Thomas Gleixner:
 "The 4.6 pile of irq updates contains:

   - Support for IPI irqdomains to support proper integration of IPIs to
     and from coprocessors.  The first user of this new facility is
     MIPS.  The relevant MIPS patches come with the core to avoid merge
     ordering issues and have been acked by Ralf.

   - A new command line option to set the default interrupt affinity
     mask at boot time.

   - Support for some more new ARM and MIPS interrupt controllers:
     tango, alpine-msix and bcm6345-l1

   - Two small cleanups for x86/apic which we merged into irq/core to
     avoid yet another branch in x86 with two tiny commits.

   - The usual set of updates, cleanups in drivers/irqchip.  Mostly in
     the area of ARM-GIC, arada-37-xp and atmel chips.  Nothing
     outstanding here"

* 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (56 commits)
  irqchip/irq-alpine-msi: Release the correct domain on error
  irqchip/mxs: Fix error check of of_io_request_and_map()
  irqchip/sunxi-nmi: Fix error check of of_io_request_and_map()
  genirq: Export IRQ functions for module use
  irqchip/gic/realview: Support more RealView DCC variants
  Documentation/bindings: Document the Alpine MSIX driver
  irqchip: Add the Alpine MSIX interrupt controller
  irqchip/gic-v3: Always return IRQ_SET_MASK_OK_DONE in gic_set_affinity
  irqchip/gic-v3-its: Mark its_init() and its children as __init
  irqchip/gic-v3: Remove gic_root_node variable from the ITS code
  irqchip/gic-v3: ACPI: Add redistributor support via GICC structures
  irqchip/gic-v3: Add ACPI support for GICv3/4 initialization
  irqchip/gic-v3: Refactor gic_of_init() for GICv3 driver
  x86/apic: Deinline _flat_send_IPI_mask, save ~150 bytes
  x86/apic: Deinline __default_send_IPI_*, save ~200 bytes
  dt-bindings: interrupt-controller: Add SoC-specific compatible string to Marvell ODMI
  irqchip/mips-gic: Add new DT property to reserve IPIs
  MIPS: Delete smp-gic.c
  MIPS: Make smp CMP, CPS and MT use the new generic IPI functions
  MIPS: Add generic SMP IPI support
  ...
parents 8a284c06 8e7fe266

Documentation/devicetree/bindings/interrupt-controller/al,alpine-msix.txt

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Alpine MSIX controller



See arm,gic-v3.txt for SPI and MSI definitions.



Required properties:



- compatible: should be "al,alpine-msix"

- reg: physical base address and size of the registers

- interrupt-parent: specifies the parent interrupt controller.

- interrupt-controller: identifies the node as an interrupt controller

- msi-controller: identifies the node as an PCI Message Signaled Interrupt

		  controller

- al,msi-base-spi: SPI base of the MSI frame

- al,msi-num-spis: number of SPIs assigned to the MSI frame, relative to SPI0



Example:



msix: msix {

	compatible = "al,alpine-msix";

	reg = <0x0 0xfbe00000 0x0 0x100000>;

	interrupt-parent = <&gic>;

	interrupt-controller;

	msi-controller;

	al,msi-base-spi = <160>;

	al,msi-num-spis = <160>;

};

Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt

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@@ -16,6 +16,7 @@ Main node required properties: 
	"arm,cortex-a15-gic"

	"arm,cortex-a7-gic"

	"arm,cortex-a9-gic"

	"arm,eb11mp-gic"

	"arm,gic-400"

	"arm,pl390"

	"arm,tc11mp-gic"

Documentation/devicetree/bindings/interrupt-controller/marvell,odmi-controller.txt

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* Marvell ODMI for MSI support



Some Marvell SoCs have an On-Die Message Interrupt (ODMI) controller

which can be used by on-board peripheral for MSI interrupts.



Required properties:



- compatible           : The value here should contain:



    "marvell,ap806-odmi-controller", "marvell,odmi-controller".



- interrupt,controller : Identifies the node as an interrupt controller.



- msi-controller       : Identifies the node as an MSI controller.



- marvell,odmi-frames  : Number of ODMI frames available. Each frame

                         provides a number of events.



- reg                  : List of register definitions, one for each

                         ODMI frame.



- marvell,spi-base     : List of GIC base SPI interrupts, one for each

                         ODMI frame. Those SPI interrupts are 0-based,

                         i.e marvell,spi-base = <128> will use SPI #96.

                         See Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt

                         for details about the GIC Device Tree binding.



- interrupt-parent     : Reference to the parent interrupt controller.



Example:



	odmi: odmi@300000 {

		compatible = "marvell,ap806-odm-controller",

			     "marvell,odmi-controller";

		interrupt-controller;

		msi-controller;

		marvell,odmi-frames = <4>;

		reg = <0x300000 0x4000>,

		      <0x304000 0x4000>,

		      <0x308000 0x4000>,

		      <0x30C000 0x4000>;

		marvell,spi-base = <128>, <136>, <144>, <152>;

	};

Documentation/devicetree/bindings/interrupt-controller/mips-gic.txt

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@@ -23,6 +23,12 @@ Optional properties: 
- mti,reserved-cpu-vectors : Specifies the list of CPU interrupt vectors

  to which the GIC may not route interrupts.  Valid values are 2 - 7.

  This property is ignored if the CPU is started in EIC mode.

- mti,reserved-ipi-vectors : Specifies the range of GIC interrupts that are

  reserved for IPIs.

  It accepts 2 values, the 1st is the starting interrupt and the 2nd is the size

  of the reserved range.

  If not specified, the driver will allocate the last 2 * number of VPEs in the

  system.



Required properties for timer sub-node:

- compatible : Should be "mti,gic-timer".
@@ -44,6 +50,7 @@ Example: 
		#interrupt-cells = <3>;



		mti,reserved-cpu-vectors = <7>;

		mti,reserved-ipi-vectors = <40 8>;



		timer {

			compatible = "mti,gic-timer";

Documentation/devicetree/bindings/interrupt-controller/sigma,smp8642-intc.txt

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Sigma Designs SMP86xx/SMP87xx secondary interrupt controller



Required properties:

- compatible: should be "sigma,smp8642-intc"

- reg: physical address of MMIO region

- ranges: address space mapping of child nodes

- interrupt-parent: phandle of parent interrupt controller

- interrupt-controller: boolean

- #address-cells: should be <1>

- #size-cells: should be <1>



One child node per control block with properties:

- reg: address of registers for this control block

- interrupt-controller: boolean

- #interrupt-cells: should be <2>, interrupt index and flags per interrupts.txt

- interrupts: interrupt spec of primary interrupt controller



Example:



interrupt-controller@6e000 {

	compatible = "sigma,smp8642-intc";

	reg = <0x6e000 0x400>;

	ranges = <0x0 0x6e000 0x400>;

	interrupt-parent = <&gic>;

	interrupt-controller;

	#address-cells = <1>;

	#size-cells = <1>;



	irq0: interrupt-controller@0 {

		reg = <0x000 0x100>;

		interrupt-controller;

		#interrupt-cells = <2>;

		interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;

	};



	irq1: interrupt-controller@100 {

		reg = <0x100 0x100>;

		interrupt-controller;

		#interrupt-cells = <2>;

		interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;

	};



	irq2: interrupt-controller@300 {

		reg = <0x300 0x100>;

		interrupt-controller;

		#interrupt-cells = <2>;

		interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;

	};

};