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Commit dd79c0be authored by Heiko Stuebner's avatar Heiko Stuebner
Browse files

clk: rockchip: add ROCKCHIP_PLL_SYNC_RATE flag to some plls 



Add the new flag to gpll and cpll on rk3188 and similar and to
gpll, cpll and npll on rk3288.

Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
Reviewed-by: default avatarKever Yang <kever.yang@rock-chips.com>
Tested-by: default avatarKever Yang <kever.yang@rock-chips.com>
parent 0bb66d3b

drivers/clk/rockchip/clk-rk3188.c

+2 −2
Original line number Diff line number Diff line
@@ -216,9 +216,9 @@ static struct rockchip_pll_clock rk3188_pll_clks[] __initdata = { 
	[dpll] = PLL(pll_rk3066, PLL_DPLL, "dpll", mux_pll_p, 0, RK2928_PLL_CON(4),

		     RK2928_MODE_CON, 4, 5, 0, NULL),

	[cpll] = PLL(pll_rk3066, PLL_CPLL, "cpll", mux_pll_p, 0, RK2928_PLL_CON(8),

		     RK2928_MODE_CON, 8, 7, 0, rk3188_pll_rates),

		     RK2928_MODE_CON, 8, 7, ROCKCHIP_PLL_SYNC_RATE, rk3188_pll_rates),

	[gpll] = PLL(pll_rk3066, PLL_GPLL, "gpll", mux_pll_p, 0, RK2928_PLL_CON(12),

		     RK2928_MODE_CON, 12, 8, 0, rk3188_pll_rates),

		     RK2928_MODE_CON, 12, 8, ROCKCHIP_PLL_SYNC_RATE, rk3188_pll_rates),

};



#define MFLAGS CLK_MUX_HIWORD_MASK

drivers/clk/rockchip/clk-rk3288.c

+3 −3
Original line number Diff line number Diff line
@@ -206,11 +206,11 @@ static struct rockchip_pll_clock rk3288_pll_clks[] __initdata = { 
	[dpll] = PLL(pll_rk3066, PLL_DPLL, "dpll", mux_pll_p, 0, RK3288_PLL_CON(4),

		     RK3288_MODE_CON, 4, 5, 0, NULL),

	[cpll] = PLL(pll_rk3066, PLL_CPLL, "cpll", mux_pll_p, 0, RK3288_PLL_CON(8),

		     RK3288_MODE_CON, 8, 7, 0, rk3288_pll_rates),

		     RK3288_MODE_CON, 8, 7, ROCKCHIP_PLL_SYNC_RATE, rk3288_pll_rates),

	[gpll] = PLL(pll_rk3066, PLL_GPLL, "gpll", mux_pll_p, 0, RK3288_PLL_CON(12),

		     RK3288_MODE_CON, 12, 8, 0, rk3288_pll_rates),

		     RK3288_MODE_CON, 12, 8, ROCKCHIP_PLL_SYNC_RATE, rk3288_pll_rates),

	[npll] = PLL(pll_rk3066, PLL_NPLL, "npll",  mux_pll_p, 0, RK3288_PLL_CON(16),

		     RK3288_MODE_CON, 14, 9, 0, rk3288_pll_rates),

		     RK3288_MODE_CON, 14, 9, ROCKCHIP_PLL_SYNC_RATE, rk3288_pll_rates),

};



static struct clk_div_table div_hclk_cpu_t[] = {