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Commit db0fe532 authored by Richard Kuo's avatar Richard Kuo
Browse files

Hexagon: add support for additional exceptions 



Add multi-reg-write and unaligned-PC exceptions.

Signed-off-by: default avatarRichard Kuo <rkuo@codeaurora.org>
parent 20f704b6

arch/hexagon/kernel/traps.c

+10 −0
Original line number Diff line number Diff line
@@ -65,6 +65,10 @@ static const char *ex_name(int ex) 
		return "Write protection fault";

	case HVM_GE_C_XMAL:

		return "Misaligned instruction";

	case HVM_GE_C_WREG:

		return "Multiple writes to same register in packet";

	case HVM_GE_C_PCAL:

		return "Program counter values that are not properly aligned";

	case HVM_GE_C_RMAL:

		return "Misaligned data load";

	case HVM_GE_C_WMAL:
@@ -324,6 +328,12 @@ void do_genex(struct pt_regs *regs) 
	case HVM_GE_C_XMAL:

		misaligned_instruction(regs);

		break;

	case HVM_GE_C_WREG:

		illegal_instruction(regs);

		break;

	case HVM_GE_C_PCAL:

		misaligned_instruction(regs);

		break;

	case HVM_GE_C_RMAL:

		misaligned_data_load(regs);

		break;