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Commit da86748b authored by Boris Brezillon's avatar Boris Brezillon
Browse files

Merge tag 'nand/for-4.19' of git://git.infradead.org/linux-mtd into mtd/next 

Pull NAND updates from Miquel Raynal:

"
 NAND core changes:
 - Add the SPI-NAND framework.
 - Create a helper to find the best ECC configuration.
 - Create NAND controller operations.
 - Allocate dynamically ONFI parameters structure.
 - Add defines for ONFI version bits.
 - Add manufacturer fixup for ONFI parameter page.
 - Add an option to specify NAND chip as a boot device.
 - Add Reed-Solomon error correction algorithm.
 - Better name for the controller structure.
 - Remove unused caller_is_module() definition.
 - Make subop helpers return unsigned values.
 - Expose _notsupp() helpers for raw page accessors.
 - Add default values for dynamic timings.
 - Kill the chip->scan_bbt() hook.
 - Rename nand_default_bbt() into nand_create_bbt().
 - Start to clean the nand_chip structure.
 - Remove stale prototype from rawnand.h.

 Raw NAND controllers drivers changes:
 - Qcom: structuring cleanup.
 - Denali: use core helper to find the best ECC configuration.
 - Possible build of almost all drivers by adding a dependency on
   COMPILE_TEST for almost all of them in Kconfig, implies various
   fixes, Kconfig cleanup, GPIO headers inclusion cleanup, and even
   changes in sparc64 and ia64 architectures.
 - Clean the ->probe() functions error path of a lot of drivers.
 - Migrate all drivers to use nand_scan() instead of
   nand_scan_ident()/nand_scan_tail() pair.
 - Use mtd_device_register() where applicable to simplify the code.
 - Marvell:
   * Handle on-die ECC.
   * Better clocks handling.
   * Remove bogus comment.
   * Add suspend and resume support.
 - Tegra: add NAND controller driver.
 - Atmel:
   * Add module param to avoid using dma.
   * Drop Wenyou Yang from MAINTAINERS.
 - Denali: optimize timings handling.
 - FSMC: Stop using chip->read_buf().
 - FSL:
   * Switch to SPDX license tag identifiers.
   * Fix qualifiers in MXC init functions.

 Raw NAND chip drivers changes:
 - Micron:
   * Add fixup for ONFI revision.
   * Update ecc_stats.corrected.
   * Make ECC activation stateful.
   * Avoid enabling/disabling ECC when it can't be disabled.
   * Get the actual number of bitflips.
   * Allow forced on-die ECC.
   * Support 8/512 on-die ECC.
   * Fix on-die ECC detection logic.
 - Hynix:
   * Fix decoding the OOB size on H27UCG8T2BTR.
   * Use ->exec_op() in hynix_nand_reg_write_op().
"
parents 76a83225 ed128e8b

Documentation/admin-guide/pm/intel_pstate.rst

+13 −3
Original line number Diff line number Diff line
@@ -324,8 +324,7 @@ Global Attributes 


``intel_pstate`` exposes several global attributes (files) in ``sysfs`` to

control its functionality at the system level.  They are located in the

``/sys/devices/system/cpu/cpufreq/intel_pstate/`` directory and affect all

CPUs.

``/sys/devices/system/cpu/intel_pstate/`` directory and affect all CPUs.



Some of them are not present if the ``intel_pstate=per_cpu_perf_limits``

argument is passed to the kernel in the command line.
@@ -379,6 +378,17 @@ argument is passed to the kernel in the command line. 
	but it affects the maximum possible value of per-policy P-state	limits

	(see `Interpretation of Policy Attributes`_ below for details).



``hwp_dynamic_boost``

	This attribute is only present if ``intel_pstate`` works in the

	`active mode with the HWP feature enabled <Active Mode With HWP_>`_ in

	the processor.  If set (equal to 1), it causes the minimum P-state limit

	to be increased dynamically for a short time whenever a task previously

	waiting on I/O is selected to run on a given logical CPU (the purpose

	of this mechanism is to improve performance).



	This setting has no effect on logical CPUs whose minimum P-state limit

	is directly set to the highest non-turbo P-state or above it.



.. _status_attr:



``status``
@@ -410,7 +420,7 @@ argument is passed to the kernel in the command line. 
	That only is supported in some configurations, though (for example, if

	the `HWP feature is enabled in the processor <Active Mode With HWP_>`_,

	the operation mode of the driver cannot be changed), and if it is not

	supported in the current configuration, writes to this attribute with

	supported in the current configuration, writes to this attribute will

	fail with an appropriate error.



Interpretation of Policy Attributes

Documentation/core-api/kernel-api.rst

+1 −1
Original line number Diff line number Diff line
@@ -284,7 +284,7 @@ Resources Management 
MTRR Handling

-------------



.. kernel-doc:: arch/x86/kernel/cpu/mtrr/main.c

.. kernel-doc:: arch/x86/kernel/cpu/mtrr/mtrr.c

   :export:



Security Framework

Documentation/devicetree/bindings/input/sprd,sc27xx-vibra.txt

0 → 100644
+23 −0
Original line number Diff line number Diff line 
Spreadtrum SC27xx PMIC Vibrator



Required properties:

- compatible: should be "sprd,sc2731-vibrator".

- reg: address of vibrator control register.



Example :



	sc2731_pmic: pmic@0 {

		compatible = "sprd,sc2731";

		reg = <0>;

		spi-max-frequency = <26000000>;

		interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-controller;

		#interrupt-cells = <2>;

		#address-cells = <1>;

		#size-cells = <0>;



		vibrator@eb4 {

			compatible = "sprd,sc2731-vibrator";

			reg = <0xeb4>;

		};

	};

Documentation/devicetree/bindings/mtd/denali-nand.txt

+5 −0
Original line number Diff line number Diff line
@@ -8,6 +8,9 @@ Required properties: 
  - reg : should contain registers location and length for data and reg.

  - reg-names: Should contain the reg names "nand_data" and "denali_reg"

  - interrupts : The interrupt number.

  - clocks: should contain phandle of the controller core clock, the bus

    interface clock, and the ECC circuit clock.

  - clock-names: should contain "nand", "nand_x", "ecc"



Optional properties:

  - nand-ecc-step-size: see nand.txt for details.  If present, the value must be
@@ -31,5 +34,7 @@ nand: nand@ff900000 { 
	compatible = "altr,socfpga-denali-nand";

	reg = <0xff900000 0x20>, <0xffb80000 0x1000>;

	reg-names = "nand_data", "denali_reg";

	clocks = <&nand_clk>, <&nand_x_clk>, <&nand_ecc_clk>;

	clock-names = "nand", "nand_x", "ecc";

	interrupts = <0 144 4>;

};

Documentation/devicetree/bindings/mtd/nand.txt

+5 −1
Original line number Diff line number Diff line
@@ -25,7 +25,7 @@ Optional NAND chip properties: 
		  Deprecated values:

		  "soft_bch": use "soft" and nand-ecc-algo instead

- nand-ecc-algo: string, algorithm of NAND ECC.

		 Supported values are: "hamming", "bch".

		 Valid values are: "hamming", "bch", "rs".

- nand-bus-width : 8 or 16 bus width if not present 8

- nand-on-flash-bbt: boolean to enable on flash bbt option if not present false
@@ -43,6 +43,10 @@ Optional NAND chip properties: 
		     This is particularly useful when only the in-band area is

		     used by the upper layers, and you want to make your NAND

		     as reliable as possible.

- nand-is-boot-medium: Whether the NAND chip is a boot medium. Drivers might use

		       this information to select ECC algorithms supported by

		       the boot ROM or similar restrictions.



- nand-rb: shall contain the native Ready/Busy ids.



The ECC strength and ECC step size properties define the correction capability