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Commit da48c9a2 authored by Anjali Singhai Jain's avatar Anjali Singhai Jain Committed by Jeff Kirsher
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i40e/i40evf: Update register.h file for X722 



Update the i40e and i40evf register.h file with the registers for X722.

Signed-off-by: default avatarAnjali Singhai Jain <anjali.singhai@intel.com>
Signed-off-by: default avatarCatherine Sullivan <catherine.sullivan@intel.com>
Tested-by: default avatarJim Young <james.m.young@intel.com>
Signed-off-by: default avatarJeff Kirsher <jeffrey.t.kirsher@intel.com>
parent e50c8d6d

drivers/net/ethernet/intel/i40e/i40e_register.h

+1930 −1

File changed.

Preview size limit exceeded, changes collapsed.

drivers/net/ethernet/intel/i40evf/i40e_register.h

+61 −1
Original line number Diff line number Diff line
@@ -3366,4 +3366,64 @@ 
#define I40E_VFQF_HREGION_OVERRIDE_ENA_7_MASK I40E_MASK(0x1, I40E_VFQF_HREGION_OVERRIDE_ENA_7_SHIFT)

#define I40E_VFQF_HREGION_REGION_7_SHIFT 29

#define I40E_VFQF_HREGION_REGION_7_MASK I40E_MASK(0x7, I40E_VFQF_HREGION_REGION_7_SHIFT)

#endif
 
#define I40E_VFINT_DYN_CTL01_WB_ON_ITR_SHIFT 30

#define I40E_VFINT_DYN_CTL01_WB_ON_ITR_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTL01_WB_ON_ITR_SHIFT)

#define I40E_VFINT_DYN_CTLN1_WB_ON_ITR_SHIFT 30

#define I40E_VFINT_DYN_CTLN1_WB_ON_ITR_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTLN1_WB_ON_ITR_SHIFT)

#define I40E_VFPE_AEQALLOC1 0x0000A400 /* Reset: VFR */

#define I40E_VFPE_AEQALLOC1_AECOUNT_SHIFT 0

#define I40E_VFPE_AEQALLOC1_AECOUNT_MASK I40E_MASK(0xFFFFFFFF, I40E_VFPE_AEQALLOC1_AECOUNT_SHIFT)

#define I40E_VFPE_CCQPHIGH1 0x00009800 /* Reset: VFR */

#define I40E_VFPE_CCQPHIGH1_PECCQPHIGH_SHIFT 0

#define I40E_VFPE_CCQPHIGH1_PECCQPHIGH_MASK I40E_MASK(0xFFFFFFFF, I40E_VFPE_CCQPHIGH1_PECCQPHIGH_SHIFT)

#define I40E_VFPE_CCQPLOW1 0x0000AC00 /* Reset: VFR */

#define I40E_VFPE_CCQPLOW1_PECCQPLOW_SHIFT 0

#define I40E_VFPE_CCQPLOW1_PECCQPLOW_MASK I40E_MASK(0xFFFFFFFF, I40E_VFPE_CCQPLOW1_PECCQPLOW_SHIFT)

#define I40E_VFPE_CCQPSTATUS1 0x0000B800 /* Reset: VFR */

#define I40E_VFPE_CCQPSTATUS1_CCQP_DONE_SHIFT 0

#define I40E_VFPE_CCQPSTATUS1_CCQP_DONE_MASK I40E_MASK(0x1, I40E_VFPE_CCQPSTATUS1_CCQP_DONE_SHIFT)

#define I40E_VFPE_CCQPSTATUS1_HMC_PROFILE_SHIFT 4

#define I40E_VFPE_CCQPSTATUS1_HMC_PROFILE_MASK I40E_MASK(0x7, I40E_VFPE_CCQPSTATUS1_HMC_PROFILE_SHIFT)

#define I40E_VFPE_CCQPSTATUS1_RDMA_EN_VFS_SHIFT 16

#define I40E_VFPE_CCQPSTATUS1_RDMA_EN_VFS_MASK I40E_MASK(0x3F, I40E_VFPE_CCQPSTATUS1_RDMA_EN_VFS_SHIFT)

#define I40E_VFPE_CCQPSTATUS1_CCQP_ERR_SHIFT 31

#define I40E_VFPE_CCQPSTATUS1_CCQP_ERR_MASK I40E_MASK(0x1, I40E_VFPE_CCQPSTATUS1_CCQP_ERR_SHIFT)

#define I40E_VFPE_CQACK1 0x0000B000 /* Reset: VFR */

#define I40E_VFPE_CQACK1_PECQID_SHIFT 0

#define I40E_VFPE_CQACK1_PECQID_MASK I40E_MASK(0x1FFFF, I40E_VFPE_CQACK1_PECQID_SHIFT)

#define I40E_VFPE_CQARM1 0x0000B400 /* Reset: VFR */

#define I40E_VFPE_CQARM1_PECQID_SHIFT 0

#define I40E_VFPE_CQARM1_PECQID_MASK I40E_MASK(0x1FFFF, I40E_VFPE_CQARM1_PECQID_SHIFT)

#define I40E_VFPE_CQPDB1 0x0000BC00 /* Reset: VFR */

#define I40E_VFPE_CQPDB1_WQHEAD_SHIFT 0

#define I40E_VFPE_CQPDB1_WQHEAD_MASK I40E_MASK(0x7FF, I40E_VFPE_CQPDB1_WQHEAD_SHIFT)

#define I40E_VFPE_CQPERRCODES1 0x00009C00 /* Reset: VFR */

#define I40E_VFPE_CQPERRCODES1_CQP_MINOR_CODE_SHIFT 0

#define I40E_VFPE_CQPERRCODES1_CQP_MINOR_CODE_MASK I40E_MASK(0xFFFF, I40E_VFPE_CQPERRCODES1_CQP_MINOR_CODE_SHIFT)

#define I40E_VFPE_CQPERRCODES1_CQP_MAJOR_CODE_SHIFT 16

#define I40E_VFPE_CQPERRCODES1_CQP_MAJOR_CODE_MASK I40E_MASK(0xFFFF, I40E_VFPE_CQPERRCODES1_CQP_MAJOR_CODE_SHIFT)

#define I40E_VFPE_CQPTAIL1 0x0000A000 /* Reset: VFR */

#define I40E_VFPE_CQPTAIL1_WQTAIL_SHIFT 0

#define I40E_VFPE_CQPTAIL1_WQTAIL_MASK I40E_MASK(0x7FF, I40E_VFPE_CQPTAIL1_WQTAIL_SHIFT)

#define I40E_VFPE_CQPTAIL1_CQP_OP_ERR_SHIFT 31

#define I40E_VFPE_CQPTAIL1_CQP_OP_ERR_MASK I40E_MASK(0x1, I40E_VFPE_CQPTAIL1_CQP_OP_ERR_SHIFT)

#define I40E_VFPE_IPCONFIG01 0x00008C00 /* Reset: VFR */

#define I40E_VFPE_IPCONFIG01_PEIPID_SHIFT 0

#define I40E_VFPE_IPCONFIG01_PEIPID_MASK I40E_MASK(0xFFFF, I40E_VFPE_IPCONFIG01_PEIPID_SHIFT)

#define I40E_VFPE_IPCONFIG01_USEENTIREIDRANGE_SHIFT 16

#define I40E_VFPE_IPCONFIG01_USEENTIREIDRANGE_MASK I40E_MASK(0x1, I40E_VFPE_IPCONFIG01_USEENTIREIDRANGE_SHIFT)

#define I40E_VFPE_MRTEIDXMASK1 0x00009000 /* Reset: VFR */

#define I40E_VFPE_MRTEIDXMASK1_MRTEIDXMASKBITS_SHIFT 0

#define I40E_VFPE_MRTEIDXMASK1_MRTEIDXMASKBITS_MASK I40E_MASK(0x1F, I40E_VFPE_MRTEIDXMASK1_MRTEIDXMASKBITS_SHIFT)

#define I40E_VFPE_RCVUNEXPECTEDERROR1 0x00009400 /* Reset: VFR */

#define I40E_VFPE_RCVUNEXPECTEDERROR1_TCP_RX_UNEXP_ERR_SHIFT 0

#define I40E_VFPE_RCVUNEXPECTEDERROR1_TCP_RX_UNEXP_ERR_MASK I40E_MASK(0xFFFFFF, I40E_VFPE_RCVUNEXPECTEDERROR1_TCP_RX_UNEXP_ERR_SHIFT)

#define I40E_VFPE_TCPNOWTIMER1 0x0000A800 /* Reset: VFR */

#define I40E_VFPE_TCPNOWTIMER1_TCP_NOW_SHIFT 0

#define I40E_VFPE_TCPNOWTIMER1_TCP_NOW_MASK I40E_MASK(0xFFFFFFFF, I40E_VFPE_TCPNOWTIMER1_TCP_NOW_SHIFT)

#define I40E_VFPE_WQEALLOC1 0x0000C000 /* Reset: VFR */

#define I40E_VFPE_WQEALLOC1_PEQPID_SHIFT 0

#define I40E_VFPE_WQEALLOC1_PEQPID_MASK I40E_MASK(0x3FFFF, I40E_VFPE_WQEALLOC1_PEQPID_SHIFT)

#define I40E_VFPE_WQEALLOC1_WQE_DESC_INDEX_SHIFT 20

#define I40E_VFPE_WQEALLOC1_WQE_DESC_INDEX_MASK I40E_MASK(0xFFF, I40E_VFPE_WQEALLOC1_WQE_DESC_INDEX_SHIFT)

#endif /* _I40E_REGISTER_H_ */