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Commit d8c3a392 authored by Maxime Ripard's avatar Maxime Ripard
Browse files

ARM: sunxi: dt: Add sample and output mmc clocks 



Add the sample and output clocks for the MMC phase support.

Signed-off-by: default avatarMaxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: default avatarChen-Yu Tsai <wens@csie.org>
Tested-by: default avatarChen-Yu Tsai <wens@csie.org>
parent 6b0b8ccf

arch/arm/boot/dts/sun4i-a10.dtsi

+52 −20
Original line number Original line Diff line number Diff line
@@ -226,35 +226,43 @@ 
		};

		};





		mmc0_clk: clk@01c20088 {

		mmc0_clk: clk@01c20088 {

			#clock-cells = <0>;

			#clock-cells = <1>;

			compatible = "allwinner,sun4i-a10-mod0-clk";

			compatible = "allwinner,sun4i-a10-mmc-clk";

			reg = <0x01c20088 0x4>;

			reg = <0x01c20088 0x4>;

			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;

			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;

			clock-output-names = "mmc0";

			clock-output-names = "mmc0",

					     "mmc0_output",

					     "mmc0_sample";

		};

		};





		mmc1_clk: clk@01c2008c {

		mmc1_clk: clk@01c2008c {

			#clock-cells = <0>;

			#clock-cells = <1>;

			compatible = "allwinner,sun4i-a10-mod0-clk";

			compatible = "allwinner,sun4i-a10-mmc-clk";

			reg = <0x01c2008c 0x4>;

			reg = <0x01c2008c 0x4>;

			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;

			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;

			clock-output-names = "mmc1";

			clock-output-names = "mmc1",

					     "mmc1_output",

					     "mmc1_sample";

		};

		};





		mmc2_clk: clk@01c20090 {

		mmc2_clk: clk@01c20090 {

			#clock-cells = <0>;

			#clock-cells = <1>;

			compatible = "allwinner,sun4i-a10-mod0-clk";

			compatible = "allwinner,sun4i-a10-mmc-clk";

			reg = <0x01c20090 0x4>;

			reg = <0x01c20090 0x4>;

			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;

			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;

			clock-output-names = "mmc2";

			clock-output-names = "mmc2",

					     "mmc2_output",

					     "mmc2_sample";

		};

		};





		mmc3_clk: clk@01c20094 {

		mmc3_clk: clk@01c20094 {

			#clock-cells = <0>;

			#clock-cells = <1>;

			compatible = "allwinner,sun4i-a10-mod0-clk";

			compatible = "allwinner,sun4i-a10-mmc-clk";

			reg = <0x01c20094 0x4>;

			reg = <0x01c20094 0x4>;

			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;

			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;

			clock-output-names = "mmc3";

			clock-output-names = "mmc3",

					     "mmc3_output",

					     "mmc3_sample";

		};

		};





		ts_clk: clk@01c20098 {

		ts_clk: clk@01c20098 {
@@ -398,8 +406,14 @@ 
		mmc0: mmc@01c0f000 {

		mmc0: mmc@01c0f000 {

			compatible = "allwinner,sun4i-a10-mmc";

			compatible = "allwinner,sun4i-a10-mmc";

			reg = <0x01c0f000 0x1000>;

			reg = <0x01c0f000 0x1000>;

			clocks = <&ahb_gates 8>, <&mmc0_clk>;

			clocks = <&ahb_gates 8>,

			clock-names = "ahb", "mmc";

				 <&mmc0_clk 0>,

				 <&mmc0_clk 1>,

				 <&mmc0_clk 2>;

			clock-names = "ahb",

				      "mmc",

				      "output",

				      "sample";

			interrupts = <32>;

			interrupts = <32>;

			status = "disabled";

			status = "disabled";

		};

		};
@@ -407,8 +421,14 @@ 
		mmc1: mmc@01c10000 {

		mmc1: mmc@01c10000 {

			compatible = "allwinner,sun4i-a10-mmc";

			compatible = "allwinner,sun4i-a10-mmc";

			reg = <0x01c10000 0x1000>;

			reg = <0x01c10000 0x1000>;

			clocks = <&ahb_gates 9>, <&mmc1_clk>;

			clocks = <&ahb_gates 9>,

			clock-names = "ahb", "mmc";

				 <&mmc1_clk 0>,

				 <&mmc1_clk 1>,

				 <&mmc1_clk 2>;

			clock-names = "ahb",

				      "mmc",

				      "output",

				      "sample";

			interrupts = <33>;

			interrupts = <33>;

			status = "disabled";

			status = "disabled";

		};

		};
@@ -416,8 +436,14 @@ 
		mmc2: mmc@01c11000 {

		mmc2: mmc@01c11000 {

			compatible = "allwinner,sun4i-a10-mmc";

			compatible = "allwinner,sun4i-a10-mmc";

			reg = <0x01c11000 0x1000>;

			reg = <0x01c11000 0x1000>;

			clocks = <&ahb_gates 10>, <&mmc2_clk>;

			clocks = <&ahb_gates 10>,

			clock-names = "ahb", "mmc";

				 <&mmc2_clk 0>,

				 <&mmc2_clk 1>,

				 <&mmc2_clk 2>;

			clock-names = "ahb",

				      "mmc",

				      "output",

				      "sample";

			interrupts = <34>;

			interrupts = <34>;

			status = "disabled";

			status = "disabled";

		};

		};
@@ -425,8 +451,14 @@ 
		mmc3: mmc@01c12000 {

		mmc3: mmc@01c12000 {

			compatible = "allwinner,sun4i-a10-mmc";

			compatible = "allwinner,sun4i-a10-mmc";

			reg = <0x01c12000 0x1000>;

			reg = <0x01c12000 0x1000>;

			clocks = <&ahb_gates 11>, <&mmc3_clk>;

			clocks = <&ahb_gates 11>,

			clock-names = "ahb", "mmc";

				 <&mmc3_clk 0>,

				 <&mmc3_clk 1>,

				 <&mmc3_clk 2>;

			clock-names = "ahb",

				      "mmc",

				      "output",

				      "sample";

			interrupts = <35>;

			interrupts = <35>;

			status = "disabled";

			status = "disabled";

		};

		};

arch/arm/boot/dts/sun5i-a10s.dtsi

+39 −15
Original line number Original line Diff line number Diff line
@@ -211,27 +211,33 @@ 
		};

		};





		mmc0_clk: clk@01c20088 {

		mmc0_clk: clk@01c20088 {

			#clock-cells = <0>;

			#clock-cells = <1>;

			compatible = "allwinner,sun4i-a10-mod0-clk";

			compatible = "allwinner,sun4i-a10-mmc-clk";

			reg = <0x01c20088 0x4>;

			reg = <0x01c20088 0x4>;

			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;

			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;

			clock-output-names = "mmc0";

			clock-output-names = "mmc0",

					     "mmc0_output",

					     "mmc0_sample";

		};

		};





		mmc1_clk: clk@01c2008c {

		mmc1_clk: clk@01c2008c {

			#clock-cells = <0>;

			#clock-cells = <1>;

			compatible = "allwinner,sun4i-a10-mod0-clk";

			compatible = "allwinner,sun4i-a10-mmc-clk";

			reg = <0x01c2008c 0x4>;

			reg = <0x01c2008c 0x4>;

			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;

			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;

			clock-output-names = "mmc1";

			clock-output-names = "mmc1",

					     "mmc1_output",

					     "mmc1_sample";

		};

		};





		mmc2_clk: clk@01c20090 {

		mmc2_clk: clk@01c20090 {

			#clock-cells = <0>;

			#clock-cells = <1>;

			compatible = "allwinner,sun4i-a10-mod0-clk";

			compatible = "allwinner,sun4i-a10-mmc-clk";

			reg = <0x01c20090 0x4>;

			reg = <0x01c20090 0x4>;

			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;

			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;

			clock-output-names = "mmc2";

			clock-output-names = "mmc2",

					     "mmc2_output",

					     "mmc2_sample";

		};

		};





		ts_clk: clk@01c20098 {

		ts_clk: clk@01c20098 {
@@ -359,8 +365,14 @@ 
		mmc0: mmc@01c0f000 {

		mmc0: mmc@01c0f000 {

			compatible = "allwinner,sun5i-a13-mmc";

			compatible = "allwinner,sun5i-a13-mmc";

			reg = <0x01c0f000 0x1000>;

			reg = <0x01c0f000 0x1000>;

			clocks = <&ahb_gates 8>, <&mmc0_clk>;

			clocks = <&ahb_gates 8>,

			clock-names = "ahb", "mmc";

				 <&mmc0_clk 0>,

				 <&mmc0_clk 1>,

				 <&mmc0_clk 2>;

			clock-names = "ahb",

				      "mmc",

				      "output",

				      "sample";

			interrupts = <32>;

			interrupts = <32>;

			status = "disabled";

			status = "disabled";

		};

		};
@@ -368,8 +380,14 @@ 
		mmc1: mmc@01c10000 {

		mmc1: mmc@01c10000 {

			compatible = "allwinner,sun5i-a13-mmc";

			compatible = "allwinner,sun5i-a13-mmc";

			reg = <0x01c10000 0x1000>;

			reg = <0x01c10000 0x1000>;

			clocks = <&ahb_gates 9>, <&mmc1_clk>;

			clocks = <&ahb_gates 9>,

			clock-names = "ahb", "mmc";

				 <&mmc1_clk 0>,

				 <&mmc1_clk 1>,

				 <&mmc1_clk 2>;

			clock-names = "ahb",

				      "mmc",

				      "output",

				      "sample";

			interrupts = <33>;

			interrupts = <33>;

			status = "disabled";

			status = "disabled";

		};

		};
@@ -377,8 +395,14 @@ 
		mmc2: mmc@01c11000 {

		mmc2: mmc@01c11000 {

			compatible = "allwinner,sun5i-a13-mmc";

			compatible = "allwinner,sun5i-a13-mmc";

			reg = <0x01c11000 0x1000>;

			reg = <0x01c11000 0x1000>;

			clocks = <&ahb_gates 10>, <&mmc2_clk>;

			clocks = <&ahb_gates 10>,

			clock-names = "ahb", "mmc";

				 <&mmc2_clk 0>,

				 <&mmc2_clk 1>,

				 <&mmc2_clk 2>;

			clock-names = "ahb",

				      "mmc",

				      "output",

				      "sample";

			interrupts = <34>;

			interrupts = <34>;

			status = "disabled";

			status = "disabled";

		};

		};

arch/arm/boot/dts/sun5i-a13.dtsi

+31 −13
Original line number Original line Diff line number Diff line
@@ -195,27 +195,33 @@ 
		};

		};





		mmc0_clk: clk@01c20088 {

		mmc0_clk: clk@01c20088 {

			#clock-cells = <0>;

			#clock-cells = <1>;

			compatible = "allwinner,sun4i-a10-mod0-clk";

			compatible = "allwinner,sun4i-a10-mmc-clk";

			reg = <0x01c20088 0x4>;

			reg = <0x01c20088 0x4>;

			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;

			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;

			clock-output-names = "mmc0";

			clock-output-names = "mmc0",

					     "mmc0_output",

					     "mmc0_sample";

		};

		};





		mmc1_clk: clk@01c2008c {

		mmc1_clk: clk@01c2008c {

			#clock-cells = <0>;

			#clock-cells = <1>;

			compatible = "allwinner,sun4i-a10-mod0-clk";

			compatible = "allwinner,sun4i-a10-mmc-clk";

			reg = <0x01c2008c 0x4>;

			reg = <0x01c2008c 0x4>;

			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;

			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;

			clock-output-names = "mmc1";

			clock-output-names = "mmc1",

					     "mmc1_output",

					     "mmc1_sample";

		};

		};





		mmc2_clk: clk@01c20090 {

		mmc2_clk: clk@01c20090 {

			#clock-cells = <0>;

			#clock-cells = <1>;

			compatible = "allwinner,sun4i-a10-mod0-clk";

			compatible = "allwinner,sun4i-a10-mmc-clk";

			reg = <0x01c20090 0x4>;

			reg = <0x01c20090 0x4>;

			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;

			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;

			clock-output-names = "mmc2";

			clock-output-names = "mmc2",

					     "mmc2_output",

					     "mmc2_sample";

		};

		};





		ts_clk: clk@01c20098 {

		ts_clk: clk@01c20098 {
@@ -327,8 +333,14 @@ 
		mmc0: mmc@01c0f000 {

		mmc0: mmc@01c0f000 {

			compatible = "allwinner,sun5i-a13-mmc";

			compatible = "allwinner,sun5i-a13-mmc";

			reg = <0x01c0f000 0x1000>;

			reg = <0x01c0f000 0x1000>;

			clocks = <&ahb_gates 8>, <&mmc0_clk>;

			clocks = <&ahb_gates 8>,

			clock-names = "ahb", "mmc";

				 <&mmc0_clk 0>,

				 <&mmc0_clk 1>,

				 <&mmc0_clk 2>;

			clock-names = "ahb",

				      "mmc",

				      "output",

				      "sample";

			interrupts = <32>;

			interrupts = <32>;

			status = "disabled";

			status = "disabled";

		};

		};
@@ -336,8 +348,14 @@ 
		mmc2: mmc@01c11000 {

		mmc2: mmc@01c11000 {

			compatible = "allwinner,sun5i-a13-mmc";

			compatible = "allwinner,sun5i-a13-mmc";

			reg = <0x01c11000 0x1000>;

			reg = <0x01c11000 0x1000>;

			clocks = <&ahb_gates 10>, <&mmc2_clk>;

			clocks = <&ahb_gates 10>,

			clock-names = "ahb", "mmc";

				 <&mmc2_clk 0>,

				 <&mmc2_clk 1>,

				 <&mmc2_clk 2>;

			clock-names = "ahb",

				      "mmc",

				      "output",

				      "sample";

			interrupts = <34>;

			interrupts = <34>;

			status = "disabled";

			status = "disabled";

		};

		};

arch/arm/boot/dts/sun6i-a31.dtsi

+52 −20
Original line number Original line Diff line number Diff line
@@ -241,35 +241,43 @@ 
		};

		};





		mmc0_clk: clk@01c20088 {

		mmc0_clk: clk@01c20088 {

			#clock-cells = <0>;

			#clock-cells = <1>;

			compatible = "allwinner,sun4i-a10-mod0-clk";

			compatible = "allwinner,sun4i-a10-mmc-clk";

			reg = <0x01c20088 0x4>;

			reg = <0x01c20088 0x4>;

			clocks = <&osc24M>, <&pll6 0>;

			clocks = <&osc24M>, <&pll6 0>;

			clock-output-names = "mmc0";

			clock-output-names = "mmc0",

					     "mmc0_output",

					     "mmc0_sample";

		};

		};





		mmc1_clk: clk@01c2008c {

		mmc1_clk: clk@01c2008c {

			#clock-cells = <0>;

			#clock-cells = <1>;

			compatible = "allwinner,sun4i-a10-mod0-clk";

			compatible = "allwinner,sun4i-a10-mmc-clk";

			reg = <0x01c2008c 0x4>;

			reg = <0x01c2008c 0x4>;

			clocks = <&osc24M>, <&pll6 0>;

			clocks = <&osc24M>, <&pll6 0>;

			clock-output-names = "mmc1";

			clock-output-names = "mmc1",

					     "mmc1_output",

					     "mmc1_sample";

		};

		};





		mmc2_clk: clk@01c20090 {

		mmc2_clk: clk@01c20090 {

			#clock-cells = <0>;

			#clock-cells = <1>;

			compatible = "allwinner,sun4i-a10-mod0-clk";

			compatible = "allwinner,sun4i-a10-mmc-clk";

			reg = <0x01c20090 0x4>;

			reg = <0x01c20090 0x4>;

			clocks = <&osc24M>, <&pll6 0>;

			clocks = <&osc24M>, <&pll6 0>;

			clock-output-names = "mmc2";

			clock-output-names = "mmc2",

					     "mmc2_output",

					     "mmc2_sample";

		};

		};





		mmc3_clk: clk@01c20094 {

		mmc3_clk: clk@01c20094 {

			#clock-cells = <0>;

			#clock-cells = <1>;

			compatible = "allwinner,sun4i-a10-mod0-clk";

			compatible = "allwinner,sun4i-a10-mmc-clk";

			reg = <0x01c20094 0x4>;

			reg = <0x01c20094 0x4>;

			clocks = <&osc24M>, <&pll6 0>;

			clocks = <&osc24M>, <&pll6 0>;

			clock-output-names = "mmc3";

			clock-output-names = "mmc3",

					     "mmc3_output",

					     "mmc3_sample";

		};

		};





		spi0_clk: clk@01c200a0 {

		spi0_clk: clk@01c200a0 {
@@ -366,8 +374,14 @@ 
		mmc0: mmc@01c0f000 {

		mmc0: mmc@01c0f000 {

			compatible = "allwinner,sun5i-a13-mmc";

			compatible = "allwinner,sun5i-a13-mmc";

			reg = <0x01c0f000 0x1000>;

			reg = <0x01c0f000 0x1000>;

			clocks = <&ahb1_gates 8>, <&mmc0_clk>;

			clocks = <&ahb1_gates 8>,

			clock-names = "ahb", "mmc";

				 <&mmc0_clk 0>,

				 <&mmc0_clk 1>,

				 <&mmc0_clk 2>;

			clock-names = "ahb",

				      "mmc",

				      "output",

				      "sample";

			resets = <&ahb1_rst 8>;

			resets = <&ahb1_rst 8>;

			reset-names = "ahb";

			reset-names = "ahb";

			interrupts = <0 60 4>;

			interrupts = <0 60 4>;
@@ -377,8 +391,14 @@ 
		mmc1: mmc@01c10000 {

		mmc1: mmc@01c10000 {

			compatible = "allwinner,sun5i-a13-mmc";

			compatible = "allwinner,sun5i-a13-mmc";

			reg = <0x01c10000 0x1000>;

			reg = <0x01c10000 0x1000>;

			clocks = <&ahb1_gates 9>, <&mmc1_clk>;

			clocks = <&ahb1_gates 9>,

			clock-names = "ahb", "mmc";

				 <&mmc1_clk 0>,

				 <&mmc1_clk 1>,

				 <&mmc1_clk 2>;

			clock-names = "ahb",

				      "mmc",

				      "output",

				      "sample";

			resets = <&ahb1_rst 9>;

			resets = <&ahb1_rst 9>;

			reset-names = "ahb";

			reset-names = "ahb";

			interrupts = <0 61 4>;

			interrupts = <0 61 4>;
@@ -388,8 +408,14 @@ 
		mmc2: mmc@01c11000 {

		mmc2: mmc@01c11000 {

			compatible = "allwinner,sun5i-a13-mmc";

			compatible = "allwinner,sun5i-a13-mmc";

			reg = <0x01c11000 0x1000>;

			reg = <0x01c11000 0x1000>;

			clocks = <&ahb1_gates 10>, <&mmc2_clk>;

			clocks = <&ahb1_gates 10>,

			clock-names = "ahb", "mmc";

				 <&mmc2_clk 0>,

				 <&mmc2_clk 1>,

				 <&mmc2_clk 2>;

			clock-names = "ahb",

				      "mmc",

				      "output",

				      "sample";

			resets = <&ahb1_rst 10>;

			resets = <&ahb1_rst 10>;

			reset-names = "ahb";

			reset-names = "ahb";

			interrupts = <0 62 4>;

			interrupts = <0 62 4>;
@@ -399,8 +425,14 @@ 
		mmc3: mmc@01c12000 {

		mmc3: mmc@01c12000 {

			compatible = "allwinner,sun5i-a13-mmc";

			compatible = "allwinner,sun5i-a13-mmc";

			reg = <0x01c12000 0x1000>;

			reg = <0x01c12000 0x1000>;

			clocks = <&ahb1_gates 11>, <&mmc3_clk>;

			clocks = <&ahb1_gates 11>,

			clock-names = "ahb", "mmc";

				 <&mmc3_clk 0>,

				 <&mmc3_clk 1>,

				 <&mmc3_clk 2>;

			clock-names = "ahb",

				      "mmc",

				      "output",

				      "sample";

			resets = <&ahb1_rst 11>;

			resets = <&ahb1_rst 11>;

			reset-names = "ahb";

			reset-names = "ahb";

			interrupts = <0 63 4>;

			interrupts = <0 63 4>;

arch/arm/boot/dts/sun7i-a20.dtsi

+52 −20
Original line number Original line Diff line number Diff line
@@ -274,35 +274,43 @@ 
		};

		};





		mmc0_clk: clk@01c20088 {

		mmc0_clk: clk@01c20088 {

			#clock-cells = <0>;

			#clock-cells = <1>;

			compatible = "allwinner,sun4i-a10-mod0-clk";

			compatible = "allwinner,sun4i-a10-mmc-clk";

			reg = <0x01c20088 0x4>;

			reg = <0x01c20088 0x4>;

			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;

			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;

			clock-output-names = "mmc0";

			clock-output-names = "mmc0",

					     "mmc0_output",

					     "mmc0_sample";

		};

		};





		mmc1_clk: clk@01c2008c {

		mmc1_clk: clk@01c2008c {

			#clock-cells = <0>;

			#clock-cells = <1>;

			compatible = "allwinner,sun4i-a10-mod0-clk";

			compatible = "allwinner,sun4i-a10-mmc-clk";

			reg = <0x01c2008c 0x4>;

			reg = <0x01c2008c 0x4>;

			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;

			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;

			clock-output-names = "mmc1";

			clock-output-names = "mmc1",

					     "mmc1_output",

					     "mmc1_sample";

		};

		};





		mmc2_clk: clk@01c20090 {

		mmc2_clk: clk@01c20090 {

			#clock-cells = <0>;

			#clock-cells = <1>;

			compatible = "allwinner,sun4i-a10-mod0-clk";

			compatible = "allwinner,sun4i-a10-mmc-clk";

			reg = <0x01c20090 0x4>;

			reg = <0x01c20090 0x4>;

			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;

			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;

			clock-output-names = "mmc2";

			clock-output-names = "mmc2",

					     "mmc2_output",

					     "mmc2_sample";

		};

		};





		mmc3_clk: clk@01c20094 {

		mmc3_clk: clk@01c20094 {

			#clock-cells = <0>;

			#clock-cells = <1>;

			compatible = "allwinner,sun4i-a10-mod0-clk";

			compatible = "allwinner,sun4i-a10-mmc-clk";

			reg = <0x01c20094 0x4>;

			reg = <0x01c20094 0x4>;

			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;

			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;

			clock-output-names = "mmc3";

			clock-output-names = "mmc3",

					     "mmc3_output",

					     "mmc3_sample";

		};

		};





		ts_clk: clk@01c20098 {

		ts_clk: clk@01c20098 {
@@ -518,8 +526,14 @@ 
		mmc0: mmc@01c0f000 {

		mmc0: mmc@01c0f000 {

			compatible = "allwinner,sun5i-a13-mmc";

			compatible = "allwinner,sun5i-a13-mmc";

			reg = <0x01c0f000 0x1000>;

			reg = <0x01c0f000 0x1000>;

			clocks = <&ahb_gates 8>, <&mmc0_clk>;

			clocks = <&ahb_gates 8>,

			clock-names = "ahb", "mmc";

				 <&mmc0_clk 0>,

				 <&mmc0_clk 1>,

				 <&mmc0_clk 2>;

			clock-names = "ahb",

				      "mmc",

				      "output",

				      "sample";

			interrupts = <0 32 4>;

			interrupts = <0 32 4>;

			status = "disabled";

			status = "disabled";

		};

		};
@@ -527,8 +541,14 @@ 
		mmc1: mmc@01c10000 {

		mmc1: mmc@01c10000 {

			compatible = "allwinner,sun5i-a13-mmc";

			compatible = "allwinner,sun5i-a13-mmc";

			reg = <0x01c10000 0x1000>;

			reg = <0x01c10000 0x1000>;

			clocks = <&ahb_gates 9>, <&mmc1_clk>;

			clocks = <&ahb_gates 9>,

			clock-names = "ahb", "mmc";

				 <&mmc1_clk 0>,

				 <&mmc1_clk 1>,

				 <&mmc1_clk 2>;

			clock-names = "ahb",

				      "mmc",

				      "output",

				      "sample";

			interrupts = <0 33 4>;

			interrupts = <0 33 4>;

			status = "disabled";

			status = "disabled";

		};

		};
@@ -536,8 +556,14 @@ 
		mmc2: mmc@01c11000 {

		mmc2: mmc@01c11000 {

			compatible = "allwinner,sun5i-a13-mmc";

			compatible = "allwinner,sun5i-a13-mmc";

			reg = <0x01c11000 0x1000>;

			reg = <0x01c11000 0x1000>;

			clocks = <&ahb_gates 10>, <&mmc2_clk>;

			clocks = <&ahb_gates 10>,

			clock-names = "ahb", "mmc";

				 <&mmc2_clk 0>,

				 <&mmc2_clk 1>,

				 <&mmc2_clk 2>;

			clock-names = "ahb",

				      "mmc",

				      "output",

				      "sample";

			interrupts = <0 34 4>;

			interrupts = <0 34 4>;

			status = "disabled";

			status = "disabled";

		};

		};
@@ -545,8 +571,14 @@ 
		mmc3: mmc@01c12000 {

		mmc3: mmc@01c12000 {

			compatible = "allwinner,sun5i-a13-mmc";

			compatible = "allwinner,sun5i-a13-mmc";

			reg = <0x01c12000 0x1000>;

			reg = <0x01c12000 0x1000>;

			clocks = <&ahb_gates 11>, <&mmc3_clk>;

			clocks = <&ahb_gates 11>,

			clock-names = "ahb", "mmc";

				 <&mmc3_clk 0>,

				 <&mmc3_clk 1>,

				 <&mmc3_clk 2>;

			clock-names = "ahb",

				      "mmc",

				      "output",

				      "sample";

			interrupts = <0 35 4>;

			interrupts = <0 35 4>;

			status = "disabled";

			status = "disabled";

		};

		};