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Commit d8609a3a authored by Stephen Boyd's avatar Stephen Boyd
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Merge tag 'imx-clk-fixes-4.6-2' of... 

Merge tag 'imx-clk-fixes-4.6-2' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into clk-next

Pull some non-critical i.MX clk fixes from Shawn Guo:

 * Fix the commit 3713e3f5 ("clk: imx35: define two clocks for rtc")
   which messed up the clock enumeration when adding new clock.

* tag 'imx-clk-fixes-4.6-2' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
  ARM: dts: imx35: restore existing used clock enumeration
  clk: imx6q: fix typo in CAN clock definition
parents 4afe2d1a 3397c2c4

Documentation/devicetree/bindings/clock/imx35-clock.txt

+1 −0
Original line number Diff line number Diff line
@@ -94,6 +94,7 @@ clocks and IDs. 
	csi_sel			79

	iim_gate		80

	gpu2d_gate		81

	ckli_gate		82



Examples:

drivers/clk/imx/clk-imx35.c

+2 −2
Original line number Diff line number Diff line
@@ -66,7 +66,7 @@ static const char *std_sel[] = {"ppll", "arm"}; 
static const char *ipg_per_sel[] = {"ahb_per_div", "arm_per_div"};



enum mx35_clks {

	ckih, ckil, mpll, ppll, mpll_075, arm, hsp, hsp_div, hsp_sel, ahb, ipg,

	ckih, mpll, ppll, mpll_075, arm, hsp, hsp_div, hsp_sel, ahb, ipg,

	arm_per_div, ahb_per_div, ipg_per, uart_sel, uart_div, esdhc_sel,

	esdhc1_div, esdhc2_div, esdhc3_div, spdif_sel, spdif_div_pre,

	spdif_div_post, ssi_sel, ssi1_div_pre, ssi1_div_post, ssi2_div_pre,
@@ -79,7 +79,7 @@ enum mx35_clks { 
	rtc_gate, rtic_gate, scc_gate, sdma_gate, spba_gate, spdif_gate,

	ssi1_gate, ssi2_gate, uart1_gate, uart2_gate, uart3_gate, usbotg_gate,

	wdog_gate, max_gate, admux_gate, csi_gate, csi_div, csi_sel, iim_gate,

	gpu2d_gate, clk_max

	gpu2d_gate, ckil, clk_max

};



static struct clk *clk[clk_max];

drivers/clk/imx/clk-imx6q.c

+1 −1
Original line number Diff line number Diff line
@@ -394,7 +394,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) 
		clk[IMX6QDL_CLK_LDB_DI1_DIV_3_5] = imx_clk_fixed_factor("ldb_di1_div_3_5", "ldb_di1", 2, 7);

	} else {

		clk[IMX6QDL_CLK_ECSPI_ROOT] = imx_clk_divider("ecspi_root", "pll3_60m", base + 0x38, 19, 6);

		clk[IMX6QDL_CLK_CAN_ROOT] = imx_clk_divider("can_root", "pll3_60", base + 0x20, 2, 6);

		clk[IMX6QDL_CLK_CAN_ROOT] = imx_clk_divider("can_root", "pll3_60m", base + 0x20, 2, 6);

		clk[IMX6QDL_CLK_IPG_PER] = imx_clk_fixup_divider("ipg_per", "ipg", base + 0x1c, 0, 6, imx_cscmr1_fixup);

		clk[IMX6QDL_CLK_UART_SERIAL_PODF] = imx_clk_divider("uart_serial_podf", "pll3_80m",          base + 0x24, 0,  6);

		clk[IMX6QDL_CLK_LDB_DI0_DIV_3_5] = imx_clk_fixed_factor("ldb_di0_div_3_5", "ldb_di0_sel", 2, 7);