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Commit d4d2c558 authored by Michael Chan's avatar Michael Chan Committed by David S. Miller
Browse files

[TG3]: Add support for 5714S and 5715S 



Add support for 5714S and 5715S.

Signed-off-by: default avatarMichael Chan <mchan@broadcom.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent d15150f7

drivers/net/tg3.c

+34 −1
Original line number Original line Diff line number Diff line
@@ -223,8 +223,12 @@ static struct pci_device_id tg3_pci_tbl[] = { 
	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },

	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },

	{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714,

	{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714,

	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },

	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },

	{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S,

	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },

	{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715,

	{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715,

	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },

	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },

	{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S,

	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },

	{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780,

	{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780,

	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },

	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },

	{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S,

	{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S,
@@ -2680,6 +2684,12 @@ static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset) 




	err |= tg3_readphy(tp, MII_BMSR, &bmsr);

	err |= tg3_readphy(tp, MII_BMSR, &bmsr);

	err |= tg3_readphy(tp, MII_BMSR, &bmsr);

	err |= tg3_readphy(tp, MII_BMSR, &bmsr);

	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {

		if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)

			bmsr |= BMSR_LSTATUS;

		else

			bmsr &= ~BMSR_LSTATUS;

	}





	err |= tg3_readphy(tp, MII_BMCR, &bmcr);

	err |= tg3_readphy(tp, MII_BMCR, &bmcr);
@@ -2748,6 +2758,13 @@ static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset) 
			bmcr = new_bmcr;

			bmcr = new_bmcr;

			err |= tg3_readphy(tp, MII_BMSR, &bmsr);

			err |= tg3_readphy(tp, MII_BMSR, &bmsr);

			err |= tg3_readphy(tp, MII_BMSR, &bmsr);

			err |= tg3_readphy(tp, MII_BMSR, &bmsr);

			if (GET_ASIC_REV(tp->pci_chip_rev_id) ==

			    ASIC_REV_5714) {

				if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)

					bmsr |= BMSR_LSTATUS;

				else

					bmsr &= ~BMSR_LSTATUS;

			}

			tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;

			tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;

		}

		}

	}

	}
@@ -5585,6 +5602,9 @@ static int tg3_reset_hw(struct tg3 *tp) 
		tg3_abort_hw(tp, 1);

		tg3_abort_hw(tp, 1);

	}

	}





	if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)

		tg3_phy_reset(tp);



	err = tg3_chip_reset(tp);

	err = tg3_chip_reset(tp);

	if (err)

	if (err)

		return err;

		return err;
@@ -6097,6 +6117,17 @@ static int tg3_reset_hw(struct tg3 *tp) 
		tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;

		tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;

	}

	}





	if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&

	    (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {

		u32 tmp;



		tmp = tr32(SERDES_RX_CTRL);

		tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);

		tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;

		tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;

		tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);

	}



	err = tg3_setup_phy(tp, 1);

	err = tg3_setup_phy(tp, 1);

	if (err)

	if (err)

		return err;

		return err;
@@ -6476,7 +6507,9 @@ static int tg3_open(struct net_device *dev) 




	if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&

	if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&

	    (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5750_AX) &&

	    (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5750_AX) &&

	    (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5750_BX)) {

	    (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5750_BX) &&

	    !((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) &&

	      (tp->pdev_peer == tp->pdev))) {

		/* All MSI supporting chips should support tagged

		/* All MSI supporting chips should support tagged

		 * status.  Assert that this is the case.

		 * status.  Assert that this is the case.

		 */

		 */

include/linux/pci_ids.h

+2 −0
Original line number Original line Diff line number Diff line
@@ -1857,12 +1857,14 @@ 
#define PCI_DEVICE_ID_TIGON3_5705M	0x165d

#define PCI_DEVICE_ID_TIGON3_5705M	0x165d

#define PCI_DEVICE_ID_TIGON3_5705M_2	0x165e

#define PCI_DEVICE_ID_TIGON3_5705M_2	0x165e

#define PCI_DEVICE_ID_TIGON3_5714	0x1668

#define PCI_DEVICE_ID_TIGON3_5714	0x1668

#define PCI_DEVICE_ID_TIGON3_5714S	0x1669

#define PCI_DEVICE_ID_TIGON3_5780	0x166a

#define PCI_DEVICE_ID_TIGON3_5780	0x166a

#define PCI_DEVICE_ID_TIGON3_5780S	0x166b

#define PCI_DEVICE_ID_TIGON3_5780S	0x166b

#define PCI_DEVICE_ID_TIGON3_5705F	0x166e

#define PCI_DEVICE_ID_TIGON3_5705F	0x166e

#define PCI_DEVICE_ID_TIGON3_5750	0x1676

#define PCI_DEVICE_ID_TIGON3_5750	0x1676

#define PCI_DEVICE_ID_TIGON3_5751	0x1677

#define PCI_DEVICE_ID_TIGON3_5751	0x1677

#define PCI_DEVICE_ID_TIGON3_5715	0x1678

#define PCI_DEVICE_ID_TIGON3_5715	0x1678

#define PCI_DEVICE_ID_TIGON3_5715S	0x1679

#define PCI_DEVICE_ID_TIGON3_5750M	0x167c

#define PCI_DEVICE_ID_TIGON3_5750M	0x167c

#define PCI_DEVICE_ID_TIGON3_5751M	0x167d

#define PCI_DEVICE_ID_TIGON3_5751M	0x167d

#define PCI_DEVICE_ID_TIGON3_5751F	0x167e

#define PCI_DEVICE_ID_TIGON3_5751F	0x167e