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Commit d45b964a authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/radeon: set the full cache bit for fences on r7xx+ 



Needed to properly flush the read caches for fences.

Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
parent 10e9ffae

drivers/gpu/drm/radeon/r600.c

+7 −6
Original line number Original line Diff line number Diff line
@@ -2706,14 +2706,17 @@ void r600_fence_ring_emit(struct radeon_device *rdev, 
			  struct radeon_fence *fence)

			  struct radeon_fence *fence)

{

{

	struct radeon_ring *ring = &rdev->ring[fence->ring];

	struct radeon_ring *ring = &rdev->ring[fence->ring];

	u32 cp_coher_cntl = PACKET3_TC_ACTION_ENA | PACKET3_VC_ACTION_ENA |

		PACKET3_SH_ACTION_ENA;



	if (rdev->family >= CHIP_RV770)

		cp_coher_cntl |= PACKET3_FULL_CACHE_ENA;





	if (rdev->wb.use_event) {

	if (rdev->wb.use_event) {

		u64 addr = rdev->fence_drv[fence->ring].gpu_addr;

		u64 addr = rdev->fence_drv[fence->ring].gpu_addr;

		/* flush read cache over gart */

		/* flush read cache over gart */

		radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));

		radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));

		radeon_ring_write(ring, PACKET3_TC_ACTION_ENA |

		radeon_ring_write(ring, cp_coher_cntl);

					PACKET3_VC_ACTION_ENA |

					PACKET3_SH_ACTION_ENA);

		radeon_ring_write(ring, 0xFFFFFFFF);

		radeon_ring_write(ring, 0xFFFFFFFF);

		radeon_ring_write(ring, 0);

		radeon_ring_write(ring, 0);

		radeon_ring_write(ring, 10); /* poll interval */

		radeon_ring_write(ring, 10); /* poll interval */
@@ -2727,9 +2730,7 @@ void r600_fence_ring_emit(struct radeon_device *rdev, 
	} else {

	} else {

		/* flush read cache over gart */

		/* flush read cache over gart */

		radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));

		radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));

		radeon_ring_write(ring, PACKET3_TC_ACTION_ENA |

		radeon_ring_write(ring, cp_coher_cntl);

					PACKET3_VC_ACTION_ENA |

					PACKET3_SH_ACTION_ENA);

		radeon_ring_write(ring, 0xFFFFFFFF);

		radeon_ring_write(ring, 0xFFFFFFFF);

		radeon_ring_write(ring, 0);

		radeon_ring_write(ring, 0);

		radeon_ring_write(ring, 10); /* poll interval */

		radeon_ring_write(ring, 10); /* poll interval */

drivers/gpu/drm/radeon/r600d.h

+1 −0
Original line number Original line Diff line number Diff line
@@ -1582,6 +1582,7 @@ 
#              define PACKET3_CP_DMA_CMD_DAIC      (1 << 29)

#              define PACKET3_CP_DMA_CMD_DAIC      (1 << 29)

#define	PACKET3_SURFACE_SYNC				0x43

#define	PACKET3_SURFACE_SYNC				0x43

#              define PACKET3_CB0_DEST_BASE_ENA    (1 << 6)

#              define PACKET3_CB0_DEST_BASE_ENA    (1 << 6)

#              define PACKET3_FULL_CACHE_ENA       (1 << 20) /* r7xx+ only */

#              define PACKET3_TC_ACTION_ENA        (1 << 23)

#              define PACKET3_TC_ACTION_ENA        (1 << 23)

#              define PACKET3_VC_ACTION_ENA        (1 << 24)

#              define PACKET3_VC_ACTION_ENA        (1 << 24)

#              define PACKET3_CB_ACTION_ENA        (1 << 25)

#              define PACKET3_CB_ACTION_ENA        (1 << 25)