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Commit d31e2e84 authored by Thor Thayer's avatar Thor Thayer Committed by Borislav Petkov
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ARM: dts: Add Altera L2 Cache and OCRAM EDAC entries 



Add the device tree entries and bindings needed to support the Altera L2
cache and On-Chip RAM EDAC. This patch relies upon an earlier patch to
declare and setup On-chip RAM properly:

  8b907c8b ("arm: dts: socfpga: Add OCRAM node")

Signed-off-by: default avatarThor Thayer <tthayer@opensource.altera.com>
Acked-by: default avatarRob Herring <robh@kernel.org>
Cc: devicetree@vger.kernel.org
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: galak@codeaurora.org
Cc: grant.likely@linaro.org
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: ijc+devicetree@hellion.org.uk
Cc: Kumar Gala <galak@codeaurora.org>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux@arm.linux.org.uk
Cc: linux-doc@vger.kernel.org
Cc: linux-edac <linux-edac@vger.kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: m.chehab@samsung.com
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Russell King <linux@arm.linux.org.uk>
Link: http://lkml.kernel.org/r/1455132384-17108-2-git-send-email-tthayer@opensource.altera.com


Signed-off-by: default avatarBorislav Petkov <bp@suse.de>
parent c3eea194

Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt

0 → 100644
+49 −0
Original line number Original line Diff line number Diff line 
Altera SoCFPGA ECC Manager

This driver uses the EDAC framework to implement the SOCFPGA ECC Manager.

The ECC Manager counts and corrects single bit errors and counts/handles

double bit errors which are uncorrectable.



Required Properties:

- compatible : Should be "altr,socfpga-ecc-manager"

- #address-cells: must be 1

- #size-cells: must be 1

- ranges : standard definition, should translate from local addresses



Subcomponents:



L2 Cache ECC

Required Properties:

- compatible : Should be "altr,socfpga-l2-ecc"

- reg : Address and size for ECC error interrupt clear registers.

- interrupts : Should be single bit error interrupt, then double bit error

	interrupt. Note the rising edge type.



On Chip RAM ECC

Required Properties:

- compatible : Should be "altr,socfpga-ocram-ecc"

- reg : Address and size for ECC error interrupt clear registers.

- iram : phandle to On-Chip RAM definition.

- interrupts : Should be single bit error interrupt, then double bit error

	interrupt. Note the rising edge type.



Example:



	eccmgr: eccmgr@ffd08140 {

		compatible = "altr,socfpga-ecc-manager";

		#address-cells = <1>;

		#size-cells = <1>;

		ranges;



		l2-ecc@ffd08140 {

			compatible = "altr,socfpga-l2-ecc";

			reg = <0xffd08140 0x4>;

			interrupts = <0 36 1>, <0 37 1>;

		};



		ocram-ecc@ffd08144 {

			compatible = "altr,socfpga-ocram-ecc";

			reg = <0xffd08144 0x4>;

			iram = <&ocram>;

			interrupts = <0 178 1>, <0 179 1>;

		};

	};

arch/arm/boot/dts/socfpga.dtsi

+20 −0
Original line number Original line Diff line number Diff line
@@ -656,6 +656,26 @@ 
			status = "disabled";

			status = "disabled";

		};

		};





		eccmgr: eccmgr@ffd08140 {

			compatible = "altr,socfpga-ecc-manager";

			#address-cells = <1>;

			#size-cells = <1>;

			ranges;



			l2-ecc@ffd08140 {

				compatible = "altr,socfpga-l2-ecc";

				reg = <0xffd08140 0x4>;

				interrupts = <0 36 1>, <0 37 1>;

			};



			ocram-ecc@ffd08144 {

				compatible = "altr,socfpga-ocram-ecc";

				reg = <0xffd08144 0x4>;

				iram = <&ocram>;

				interrupts = <0 178 1>, <0 179 1>;

			};

		};



		L2: l2-cache@fffef000 {

		L2: l2-cache@fffef000 {

			compatible = "arm,pl310-cache";

			compatible = "arm,pl310-cache";

			reg = <0xfffef000 0x1000>;

			reg = <0xfffef000 0x1000>;