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Commit cfcfb65a authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-msm-next-2017-08-22' of git://people.freedesktop.org/~robclark/linux into drm-next 

Updates for 4.14..  I have some further patches from Jordan to add
multiple priority levels and pre-emption, but those will probably be
for 4.15 to give me time for the mesa parts.

* tag 'drm-msm-next-2017-08-22' of git://people.freedesktop.org/~robclark/linux:
  drm/msm/mdp5: mark runtime_pm functions as __maybe_unused
  drm/msm: remove unused variable
  drm/msm/mdp5: make helper function static
  drm/msm: make msm_framebuffer_init() static
  drm/msm: add helper to allocate stolen fb
  drm/msm: don't track fbdev's gem object separately
  drm/msm: add modeset module param
  drm/msm/mdp5: add tracking for clk enable-count
  drm/msm: remove unused define
  drm/msm: Add a helper function for in-kernel buffer allocations
  drm/msm: Attach the GPU MMU when it is created
  drm/msm: Add A5XX hardware fault detection
  drm/msm: Remove uneeded platform dev members
  drm/msm/mdp5: Set up runtime PM for MDSS
  drm/msm/mdp5: Write to SMP registers even if allocations don't change
  drm/msm/mdp5: Don't use mode_set helper funcs for encoders and CRTCs
  drm/msm/dsi: Implement RPM suspend/resume callbacks
  drm/msm/dsi: Set up runtime PM for DSI
  drm/msm/hdmi: Set up runtime PM for HDMI
  drm/msm/mdp5: Use runtime PM get/put API instead of toggling clocks
parents 7c0059dd d1f08d82

drivers/gpu/drm/msm/adreno/a3xx_gpu.c

+0 −2
Original line number Diff line number Diff line
@@ -486,8 +486,6 @@ struct msm_gpu *a3xx_gpu_init(struct drm_device *dev) 
	adreno_gpu = &a3xx_gpu->base;

	gpu = &adreno_gpu->base;



	a3xx_gpu->pdev = pdev;



	gpu->perfcntrs = perfcntrs;

	gpu->num_perfcntrs = ARRAY_SIZE(perfcntrs);

drivers/gpu/drm/msm/adreno/a3xx_gpu.h

+0 −1
Original line number Diff line number Diff line
@@ -28,7 +28,6 @@ 


struct a3xx_gpu {

	struct adreno_gpu base;

	struct platform_device *pdev;



	/* if OCMEM is used for GMEM: */

	uint32_t ocmem_base;

drivers/gpu/drm/msm/adreno/a4xx_gpu.c

+0 −2
Original line number Diff line number Diff line
@@ -568,8 +568,6 @@ struct msm_gpu *a4xx_gpu_init(struct drm_device *dev) 
	adreno_gpu = &a4xx_gpu->base;

	gpu = &adreno_gpu->base;



	a4xx_gpu->pdev = pdev;



	gpu->perfcntrs = NULL;

	gpu->num_perfcntrs = 0;

drivers/gpu/drm/msm/adreno/a4xx_gpu.h

+0 −1
Original line number Diff line number Diff line
@@ -23,7 +23,6 @@ 


struct a4xx_gpu {

	struct adreno_gpu base;

	struct platform_device *pdev;



	/* if OCMEM is used for GMEM: */

	uint32_t ocmem_base;

drivers/gpu/drm/msm/adreno/a5xx_gpu.c

+30 −21
Original line number Diff line number Diff line
@@ -284,28 +284,14 @@ static int a5xx_me_init(struct msm_gpu *gpu) 
static struct drm_gem_object *a5xx_ucode_load_bo(struct msm_gpu *gpu,

		const struct firmware *fw, u64 *iova)

{

	struct drm_device *drm = gpu->dev;

	struct drm_gem_object *bo;

	void *ptr;



	bo = msm_gem_new_locked(drm, fw->size - 4, MSM_BO_UNCACHED);

	if (IS_ERR(bo))

		return bo;



	ptr = msm_gem_get_vaddr(bo);

	if (!ptr) {

		drm_gem_object_unreference(bo);

		return ERR_PTR(-ENOMEM);

	}



	if (iova) {

		int ret = msm_gem_get_iova(bo, gpu->aspace, iova);

	ptr = msm_gem_kernel_new_locked(gpu->dev, fw->size - 4,

		MSM_BO_UNCACHED | MSM_BO_GPU_READONLY, gpu->aspace, &bo, iova);



		if (ret) {

			drm_gem_object_unreference(bo);

			return ERR_PTR(ret);

		}

	}

	if (IS_ERR(ptr))

		return ERR_CAST(ptr);



	memcpy(ptr, &fw->data[4], fw->size - 4);
@@ -372,8 +358,7 @@ static int a5xx_zap_shader_init(struct msm_gpu *gpu) 
{

	static bool loaded;

	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);

	struct a5xx_gpu *a5xx_gpu = to_a5xx_gpu(adreno_gpu);

	struct platform_device *pdev = a5xx_gpu->pdev;

	struct platform_device *pdev = gpu->pdev;

	int ret;



	/*
@@ -410,6 +395,7 @@ static int a5xx_zap_shader_init(struct msm_gpu *gpu) 
	  A5XX_RBBM_INT_0_MASK_RBBM_ETS_MS_TIMEOUT | \

	  A5XX_RBBM_INT_0_MASK_RBBM_ATB_ASYNC_OVERFLOW | \

	  A5XX_RBBM_INT_0_MASK_CP_HW_ERROR | \

	  A5XX_RBBM_INT_0_MASK_MISC_HANG_DETECT | \

	  A5XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS | \

	  A5XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS | \

	  A5XX_RBBM_INT_0_MASK_GPMU_VOLTAGE_DROOP)
@@ -812,6 +798,27 @@ static void a5xx_gpmu_err_irq(struct msm_gpu *gpu) 
	dev_err_ratelimited(gpu->dev->dev, "GPMU | voltage droop\n");

}



static void a5xx_fault_detect_irq(struct msm_gpu *gpu)

{

	struct drm_device *dev = gpu->dev;

	struct msm_drm_private *priv = dev->dev_private;



	dev_err(dev->dev, "gpu fault fence %x status %8.8X rb %4.4x/%4.4x ib1 %16.16llX/%4.4x ib2 %16.16llX/%4.4x\n",

		gpu->funcs->last_fence(gpu),

		gpu_read(gpu, REG_A5XX_RBBM_STATUS),

		gpu_read(gpu, REG_A5XX_CP_RB_RPTR),

		gpu_read(gpu, REG_A5XX_CP_RB_WPTR),

		gpu_read64(gpu, REG_A5XX_CP_IB1_BASE, REG_A5XX_CP_IB1_BASE_HI),

		gpu_read(gpu, REG_A5XX_CP_IB1_BUFSZ),

		gpu_read64(gpu, REG_A5XX_CP_IB2_BASE, REG_A5XX_CP_IB2_BASE_HI),

		gpu_read(gpu, REG_A5XX_CP_IB2_BUFSZ));



	/* Turn off the hangcheck timer to keep it from bothering us */

	del_timer(&gpu->hangcheck_timer);



	queue_work(priv->wq, &gpu->recover_work);

}



#define RBBM_ERROR_MASK \

	(A5XX_RBBM_INT_0_MASK_RBBM_AHB_ERROR | \

	A5XX_RBBM_INT_0_MASK_RBBM_TRANSFER_TIMEOUT | \
@@ -838,6 +845,9 @@ static irqreturn_t a5xx_irq(struct msm_gpu *gpu) 
	if (status & A5XX_RBBM_INT_0_MASK_CP_HW_ERROR)

		a5xx_cp_err_irq(gpu);



	if (status & A5XX_RBBM_INT_0_MASK_MISC_HANG_DETECT)

		a5xx_fault_detect_irq(gpu);



	if (status & A5XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS)

		a5xx_uche_err_irq(gpu);
@@ -1015,7 +1025,6 @@ struct msm_gpu *a5xx_gpu_init(struct drm_device *dev) 
	adreno_gpu = &a5xx_gpu->base;

	gpu = &adreno_gpu->base;



	a5xx_gpu->pdev = pdev;

	adreno_gpu->registers = a5xx_registers;

	adreno_gpu->reg_offsets = a5xx_register_offsets;