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Commit ce7b30e0 authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/radeon/dpm/rs780: add some sanity checking to sclk scaling 



Since the clock scaling is based on fb divider adjustments,
make sure the other pll parameters are the same.

Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Reviewed-by: default avatarChristian König <christian.koenig@amd.com>
parent c3eaa088

drivers/gpu/drm/radeon/rs780_dpm.c

+6 −0
Original line number Diff line number Diff line
@@ -449,6 +449,12 @@ static int rs780_set_engine_clock_scaling(struct radeon_device *rdev, 
	if (ret)

		return ret;



	if ((min_dividers.ref_div != max_dividers.ref_div) ||

	    (min_dividers.post_div != max_dividers.post_div) ||

	    (max_dividers.ref_div != current_max_dividers.ref_div) ||

	    (max_dividers.post_div != current_max_dividers.post_div))

		return -EINVAL;



	rs780_force_fbdiv(rdev, max_dividers.fb_div);



	if (max_dividers.fb_div > min_dividers.fb_div) {