Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit c80851f6 authored by Frederick Lawler's avatar Frederick Lawler Committed by Bjorn Helgaas
Browse files

PCI: Add PCI_EXP_LNKCTL2_TLS* macros 



The Link Control 2 register is missing macros for Target Link Speeds.  Add
those in.

Signed-off-by: default avatarFrederick Lawler <fred@fredlawl.com>
[bhelgaas: use "GT" instead of "GB"]
Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
parent 60cc43fc

include/uapi/linux/pci_regs.h

+5 −0
Original line number Diff line number Diff line
@@ -655,6 +655,11 @@ 
#define  PCI_EXP_LNKCAP2_SLS_16_0GB	0x00000010 /* Supported Speed 16GT/s */

#define  PCI_EXP_LNKCAP2_CROSSLINK	0x00000100 /* Crosslink supported */

#define PCI_EXP_LNKCTL2		48	/* Link Control 2 */

#define PCI_EXP_LNKCTL2_TLS		0x000f

#define PCI_EXP_LNKCTL2_TLS_2_5GT	0x0001 /* Supported Speed 2.5GT/s */

#define PCI_EXP_LNKCTL2_TLS_5_0GT	0x0002 /* Supported Speed 5GT/s */

#define PCI_EXP_LNKCTL2_TLS_8_0GT	0x0003 /* Supported Speed 8GT/s */

#define PCI_EXP_LNKCTL2_TLS_16_0GT	0x0004 /* Supported Speed 16GT/s */

#define PCI_EXP_LNKSTA2		50	/* Link Status 2 */

#define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2	52	/* v2 endpoints with link end here */

#define PCI_EXP_SLTCAP2		52	/* Slot Capabilities 2 */