Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit c5fc9cf2 authored by Katsuhiro Suzuki's avatar Katsuhiro Suzuki Committed by Stephen Boyd
Browse files

clk: uniphier: add LD11/LD20 stream demux system clock 



Add clock for MPEG2 transport stream I/O and demux system (HSC) on
UniPhier LD11/LD20 SoCs.

Signed-off-by: default avatarKatsuhiro Suzuki <suzuki.katsuhiro@socionext.com>
Acked-by: default avatarMasahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent 60cc43fc

drivers/clk/uniphier/clk-uniphier-sys.c

+5 −0
Original line number Diff line number Diff line
@@ -51,6 +51,9 @@ 
#define UNIPHIER_LD11_SYS_CLK_STDMAC(idx)				\

	UNIPHIER_CLK_GATE("stdmac", (idx), NULL, 0x210c, 8)



#define UNIPHIER_LD11_SYS_CLK_HSC(idx)					\

	UNIPHIER_CLK_GATE("hsc", (idx), NULL, 0x210c, 9)



#define UNIPHIER_PRO4_SYS_CLK_GIO(idx)					\

	UNIPHIER_CLK_GATE("gio", (idx), NULL, 0x2104, 6)
@@ -182,6 +185,7 @@ const struct uniphier_clk_data uniphier_ld11_sys_clk_data[] = { 
	/* Index 5 reserved for eMMC PHY */

	UNIPHIER_LD11_SYS_CLK_ETHER(6),

	UNIPHIER_LD11_SYS_CLK_STDMAC(8),			/* HSC, MIO */

	UNIPHIER_LD11_SYS_CLK_HSC(9),

	UNIPHIER_CLK_FACTOR("usb2", -1, "ref", 24, 25),

	UNIPHIER_LD11_SYS_CLK_AIO(40),

	UNIPHIER_LD11_SYS_CLK_EVEA(41),
@@ -215,6 +219,7 @@ const struct uniphier_clk_data uniphier_ld20_sys_clk_data[] = { 
	UNIPHIER_LD20_SYS_CLK_SD,

	UNIPHIER_LD11_SYS_CLK_ETHER(6),

	UNIPHIER_LD11_SYS_CLK_STDMAC(8),			/* HSC */

	UNIPHIER_LD11_SYS_CLK_HSC(9),

	/* GIO is always clock-enabled: no function for 0x210c bit5 */

	/*

	 * clock for USB Link is enabled by the logic "OR" of bit 14 and bit 15.