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Commit c3a1c9c7 authored by Russell King's avatar Russell King Committed by Dan Williams
Browse files

iop: Make IOP ATU window debug readable 



Make the inbound and outbound memory windows debugging meaningful to
those who don't know what the register names for the ATU mean.  IOW,
use plain english rather than register jargon.

Cc: Lennert Buytenhek <kernel@wantstofly.org>
Acked-by: default avatarDan Williams <dan.j.williams@intel.com>
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent 5254149f

arch/arm/plat-iop/pci.c

+20 −15
Original line number Original line Diff line number Diff line
@@ -329,23 +329,28 @@ void __init iop3xx_pci_preinit(void) 
		iop3xx_atu_setup();

		iop3xx_atu_setup();

	}

	}





	DBG("PCI:  Intel 803xx PCI init code.\n");

	DBG("PCI: Intel IOP3xx PCI init.\n");

	DBG("ATU: IOP3XX_ATUCMD=0x%04x\n", *IOP3XX_ATUCMD);

	DBG("PCI: Outbound memory window 0: PCI 0x%08x%08x\n",

	DBG("ATU: IOP3XX_OMWTVR0=0x%04x, IOP3XX_OIOWTVR=0x%04x\n",

		*IOP3XX_OUMWTVR0, *IOP3XX_OMWTVR0);

			*IOP3XX_OMWTVR0,

	DBG("PCI: Outbound memory window 1: PCI 0x%08x%08x\n",

		*IOP3XX_OUMWTVR1, *IOP3XX_OMWTVR1);

	DBG("PCI: Outbound IO window: PCI 0x%08x\n",

		*IOP3XX_OIOWTVR);

		*IOP3XX_OIOWTVR);



	DBG("PCI: Inbound memory window 0: PCI 0x%08x%08x 0x%08x -> 0x%08x\n",

		*IOP3XX_IAUBAR0, *IOP3XX_IABAR0, *IOP3XX_IALR0, *IOP3XX_IATVR0);

	DBG("PCI: Inbound memory window 1: PCI 0x%08x%08x 0x%08x\n",

		*IOP3XX_IAUBAR1, *IOP3XX_IABAR1, *IOP3XX_IALR1);

	DBG("PCI: Inbound memory window 2: PCI 0x%08x%08x 0x%08x -> 0x%08x\n",

		*IOP3XX_IAUBAR2, *IOP3XX_IABAR2, *IOP3XX_IALR2, *IOP3XX_IATVR2);

	DBG("PCI: Inbound memory window 3: PCI 0x%08x%08x 0x%08x -> 0x%08x\n",

		*IOP3XX_IAUBAR3, *IOP3XX_IABAR3, *IOP3XX_IALR3, *IOP3XX_IATVR3);



	DBG("PCI: Expansion ROM window: PCI 0x%08x%08x 0x%08x -> 0x%08x\n",

		0, *IOP3XX_ERBAR, *IOP3XX_ERLR, *IOP3XX_ERTVR);



	DBG("ATU: IOP3XX_ATUCMD=0x%04x\n", *IOP3XX_ATUCMD);

	DBG("ATU: IOP3XX_ATUCR=0x%08x\n", *IOP3XX_ATUCR);

	DBG("ATU: IOP3XX_ATUCR=0x%08x\n", *IOP3XX_ATUCR);

	DBG("ATU: IOP3XX_IABAR0=0x%08x IOP3XX_IALR0=0x%08x IOP3XX_IATVR0=%08x\n",

			*IOP3XX_IABAR0, *IOP3XX_IALR0, *IOP3XX_IATVR0);

	DBG("ATU: IOP3XX_OMWTVR0=0x%08x\n", *IOP3XX_OMWTVR0);

	DBG("ATU: IOP3XX_IABAR1=0x%08x IOP3XX_IALR1=0x%08x\n",

			*IOP3XX_IABAR1, *IOP3XX_IALR1);

	DBG("ATU: IOP3XX_ERBAR=0x%08x IOP3XX_ERLR=0x%08x IOP3XX_ERTVR=%08x\n",

			*IOP3XX_ERBAR, *IOP3XX_ERLR, *IOP3XX_ERTVR);

	DBG("ATU: IOP3XX_IABAR2=0x%08x IOP3XX_IALR2=0x%08x IOP3XX_IATVR2=%08x\n",

			*IOP3XX_IABAR2, *IOP3XX_IALR2, *IOP3XX_IATVR2);

	DBG("ATU: IOP3XX_IABAR3=0x%08x IOP3XX_IALR3=0x%08x IOP3XX_IATVR3=%08x\n",

			*IOP3XX_IABAR3, *IOP3XX_IALR3, *IOP3XX_IATVR3);





	hook_fault_code(16+6, iop3xx_pci_abort, SIGBUS, "imprecise external abort");

	hook_fault_code(16+6, iop3xx_pci_abort, SIGBUS, "imprecise external abort");

}

}