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Commit c3735aeb authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge branch 'drm-fixes-3.17' of git://people.freedesktop.org/~agd5f/linux 

more radeon fixes

* 'drm-fixes-3.17' of git://people.freedesktop.org/~agd5f/linux:
  Revert "drm/radeon: Use write-combined CPU mappings of ring buffers with PCIe"
  drm/radeon: fix active_cu mask on SI and CIK after re-init (v3)
  drm/radeon: fix active cu count for SI and CIK
  drm/radeon: re-enable selective GPUVM flushing
  drm/radeon: Sync ME and PFP after CP semaphore waits v4
  drm/radeon: fix display handling in radeon_gpu_reset
  drm/radeon: fix pm handling in radeon_gpu_reset
  drm/radeon: Only flush HDP cache for indirect buffers from userspace
  drm/radeon: properly document reloc priority mask
parents c39502c5 b738ca5d

drivers/gpu/drm/radeon/cik.c

+25 −9
Original line number Diff line number Diff line
@@ -3483,7 +3483,7 @@ static void cik_gpu_init(struct radeon_device *rdev) 
	u32 mc_shared_chmap, mc_arb_ramcfg;

	u32 hdp_host_path_cntl;

	u32 tmp;

	int i, j, k;

	int i, j;



	switch (rdev->family) {

	case CHIP_BONAIRE:
@@ -3672,14 +3672,13 @@ static void cik_gpu_init(struct radeon_device *rdev) 
		     rdev->config.cik.max_sh_per_se,

		     rdev->config.cik.max_backends_per_se);



	rdev->config.cik.active_cus = 0;

	for (i = 0; i < rdev->config.cik.max_shader_engines; i++) {

		for (j = 0; j < rdev->config.cik.max_sh_per_se; j++) {

			for (k = 0; k < rdev->config.cik.max_cu_per_sh; k++) {

			rdev->config.cik.active_cus +=

				hweight32(cik_get_cu_active_bitmap(rdev, i, j));

		}

	}

	}



	/* set HW defaults for 3D engine */

	WREG32(CP_MEQ_THRESHOLDS, MEQ1_START(0x30) | MEQ2_START(0x60));
@@ -3801,7 +3800,7 @@ int cik_ring_test(struct radeon_device *rdev, struct radeon_ring *ring) 
	radeon_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));

	radeon_ring_write(ring, ((scratch - PACKET3_SET_UCONFIG_REG_START) >> 2));

	radeon_ring_write(ring, 0xDEADBEEF);

	radeon_ring_unlock_commit(rdev, ring);

	radeon_ring_unlock_commit(rdev, ring, false);



	for (i = 0; i < rdev->usec_timeout; i++) {

		tmp = RREG32(scratch);
@@ -3920,6 +3919,17 @@ void cik_fence_compute_ring_emit(struct radeon_device *rdev, 
	radeon_ring_write(ring, 0);

}



/**

 * cik_semaphore_ring_emit - emit a semaphore on the CP ring

 *

 * @rdev: radeon_device pointer

 * @ring: radeon ring buffer object

 * @semaphore: radeon semaphore object

 * @emit_wait: Is this a sempahore wait?

 *

 * Emits a semaphore signal/wait packet to the CP ring and prevents the PFP

 * from running ahead of semaphore waits.

 */

bool cik_semaphore_ring_emit(struct radeon_device *rdev,

			     struct radeon_ring *ring,

			     struct radeon_semaphore *semaphore,
@@ -3932,6 +3942,12 @@ bool cik_semaphore_ring_emit(struct radeon_device *rdev, 
	radeon_ring_write(ring, lower_32_bits(addr));

	radeon_ring_write(ring, (upper_32_bits(addr) & 0xffff) | sel);



	if (emit_wait && ring->idx == RADEON_RING_TYPE_GFX_INDEX) {

		/* Prevent the PFP from running ahead of the semaphore wait */

		radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));

		radeon_ring_write(ring, 0x0);

	}



	return true;

}
@@ -4004,7 +4020,7 @@ int cik_copy_cpdma(struct radeon_device *rdev, 
		return r;

	}



	radeon_ring_unlock_commit(rdev, ring);

	radeon_ring_unlock_commit(rdev, ring, false);

	radeon_semaphore_free(rdev, &sem, *fence);



	return r;
@@ -4103,7 +4119,7 @@ int cik_ib_test(struct radeon_device *rdev, struct radeon_ring *ring) 
	ib.ptr[1] = ((scratch - PACKET3_SET_UCONFIG_REG_START) >> 2);

	ib.ptr[2] = 0xDEADBEEF;

	ib.length_dw = 3;

	r = radeon_ib_schedule(rdev, &ib, NULL);

	r = radeon_ib_schedule(rdev, &ib, NULL, false);

	if (r) {

		radeon_scratch_free(rdev, scratch);

		radeon_ib_free(rdev, &ib);
@@ -4324,7 +4340,7 @@ static int cik_cp_gfx_start(struct radeon_device *rdev) 
	radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */

	radeon_ring_write(ring, 0x00000010); /* VGT_OUT_DEALLOC_CNTL */



	radeon_ring_unlock_commit(rdev, ring);

	radeon_ring_unlock_commit(rdev, ring, false);



	return 0;

}

drivers/gpu/drm/radeon/cik_sdma.c

+3 −3
Original line number Diff line number Diff line
@@ -596,7 +596,7 @@ int cik_copy_dma(struct radeon_device *rdev, 
		return r;

	}



	radeon_ring_unlock_commit(rdev, ring);

	radeon_ring_unlock_commit(rdev, ring, false);

	radeon_semaphore_free(rdev, &sem, *fence);



	return r;
@@ -638,7 +638,7 @@ int cik_sdma_ring_test(struct radeon_device *rdev, 
	radeon_ring_write(ring, upper_32_bits(rdev->vram_scratch.gpu_addr));

	radeon_ring_write(ring, 1); /* number of DWs to follow */

	radeon_ring_write(ring, 0xDEADBEEF);

	radeon_ring_unlock_commit(rdev, ring);

	radeon_ring_unlock_commit(rdev, ring, false);



	for (i = 0; i < rdev->usec_timeout; i++) {

		tmp = readl(ptr);
@@ -695,7 +695,7 @@ int cik_sdma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring) 
	ib.ptr[4] = 0xDEADBEEF;

	ib.length_dw = 5;



	r = radeon_ib_schedule(rdev, &ib, NULL);

	r = radeon_ib_schedule(rdev, &ib, NULL, false);

	if (r) {

		radeon_ib_free(rdev, &ib);

		DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);

drivers/gpu/drm/radeon/evergreen.c

+2 −2
Original line number Diff line number Diff line
@@ -2869,7 +2869,7 @@ static int evergreen_cp_start(struct radeon_device *rdev) 
	radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));

	radeon_ring_write(ring, 0);

	radeon_ring_write(ring, 0);

	radeon_ring_unlock_commit(rdev, ring);

	radeon_ring_unlock_commit(rdev, ring, false);



	cp_me = 0xff;

	WREG32(CP_ME_CNTL, cp_me);
@@ -2912,7 +2912,7 @@ static int evergreen_cp_start(struct radeon_device *rdev) 
	radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */

	radeon_ring_write(ring, 0x00000010); /*  */



	radeon_ring_unlock_commit(rdev, ring);

	radeon_ring_unlock_commit(rdev, ring, false);



	return 0;

}

drivers/gpu/drm/radeon/evergreen_dma.c

+1 −1
Original line number Diff line number Diff line
@@ -155,7 +155,7 @@ int evergreen_copy_dma(struct radeon_device *rdev, 
		return r;

	}



	radeon_ring_unlock_commit(rdev, ring);

	radeon_ring_unlock_commit(rdev, ring, false);

	radeon_semaphore_free(rdev, &sem, *fence);



	return r;

drivers/gpu/drm/radeon/ni.c

+2 −2
Original line number Diff line number Diff line
@@ -1505,7 +1505,7 @@ static int cayman_cp_start(struct radeon_device *rdev) 
	radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));

	radeon_ring_write(ring, 0);

	radeon_ring_write(ring, 0);

	radeon_ring_unlock_commit(rdev, ring);

	radeon_ring_unlock_commit(rdev, ring, false);



	cayman_cp_enable(rdev, true);
@@ -1547,7 +1547,7 @@ static int cayman_cp_start(struct radeon_device *rdev) 
	radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */

	radeon_ring_write(ring, 0x00000010); /*  */



	radeon_ring_unlock_commit(rdev, ring);

	radeon_ring_unlock_commit(rdev, ring, false);



	/* XXX init other rings */