Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit c3310fbb authored by Thomas Abraham's avatar Thomas Abraham Committed by Kukjin Kim
Browse files

serial: samsung: remove all uses of get_clksrc and set_clksrc 



With clkdev based clock lookup support, the clock set and get operation
using clock names communicated between the samsung uart driver and the
SoC specific extension can be removed.

In addition to that, for each platform specific extension, add the
default clock selection, number of clock options for uart baud generator,
clock selection bit mask and shift values which is required by the
clkdev support in samsung uart driver.

The default clock selection value 'def_clk_sel' specifies the default clock
to be used as the source clock for baud rate generator in case the platform
code does not specify the same.

Cc: Ben Dooks <ben-linux@fluff.org>
Signed-off-by: default avatarThomas Abraham <thomas.abraham@linaro.org>
Signed-off-by: default avatarKukjin Kim <kgene.kim@samsung.com>
parent afba7f91

arch/arm/mach-exynos/init.c

+1 −3
Original line number Original line Diff line number Diff line
@@ -20,10 +20,8 @@ void __init exynos4_common_init_uarts(struct s3c2410_uartcfg *cfg, int no) 
	struct s3c2410_uartcfg *tcfg = cfg;

	struct s3c2410_uartcfg *tcfg = cfg;

	u32 ucnt;

	u32 ucnt;





	for (ucnt = 0; ucnt < no; ucnt++, tcfg++) {

	for (ucnt = 0; ucnt < no; ucnt++, tcfg++)

		tcfg->has_fracval = 1;

		tcfg->has_fracval = 1;

		tcfg->flags |= NO_NEED_CHECK_CLKSRC;

	}





	s3c24xx_init_uartdevs("s5pv210-uart", s5p_uart_resources, cfg, no);

	s3c24xx_init_uartdevs("s5pv210-uart", s5p_uart_resources, cfg, no);

}
 
}

arch/arm/plat-samsung/include/plat/regs-serial.h

+6 −1
Original line number Original line Diff line number Diff line
@@ -71,6 +71,7 @@ 
#define S3C2410_LCON_IRM          (1<<6)

#define S3C2410_LCON_IRM          (1<<6)





#define S3C2440_UCON_CLKMASK	  (3<<10)

#define S3C2440_UCON_CLKMASK	  (3<<10)

#define S3C2440_UCON_CLKSHIFT	  (10)

#define S3C2440_UCON_PCLK	  (0<<10)

#define S3C2440_UCON_PCLK	  (0<<10)

#define S3C2440_UCON_UCLK	  (1<<10)

#define S3C2440_UCON_UCLK	  (1<<10)

#define S3C2440_UCON_PCLK2	  (2<<10)

#define S3C2440_UCON_PCLK2	  (2<<10)
@@ -78,6 +79,7 @@ 
#define S3C2443_UCON_EPLL	  (3<<10)

#define S3C2443_UCON_EPLL	  (3<<10)





#define S3C6400_UCON_CLKMASK	(3<<10)

#define S3C6400_UCON_CLKMASK	(3<<10)

#define S3C6400_UCON_CLKSHIFT	(10)

#define S3C6400_UCON_PCLK	(0<<10)

#define S3C6400_UCON_PCLK	(0<<10)

#define S3C6400_UCON_PCLK2	(2<<10)

#define S3C6400_UCON_PCLK2	(2<<10)

#define S3C6400_UCON_UCLK0	(1<<10)

#define S3C6400_UCON_UCLK0	(1<<10)
@@ -90,11 +92,14 @@ 
#define S3C2440_UCON_DIVSHIFT	  (12)

#define S3C2440_UCON_DIVSHIFT	  (12)





#define S3C2412_UCON_CLKMASK	(3<<10)

#define S3C2412_UCON_CLKMASK	(3<<10)

#define S3C2412_UCON_CLKSHIFT	(10)

#define S3C2412_UCON_UCLK	(1<<10)

#define S3C2412_UCON_UCLK	(1<<10)

#define S3C2412_UCON_USYSCLK	(3<<10)

#define S3C2412_UCON_USYSCLK	(3<<10)

#define S3C2412_UCON_PCLK	(0<<10)

#define S3C2412_UCON_PCLK	(0<<10)

#define S3C2412_UCON_PCLK2	(2<<10)

#define S3C2412_UCON_PCLK2	(2<<10)





#define S3C2410_UCON_CLKMASK	(1 << 10)

#define S3C2410_UCON_CLKSHIFT	(10)

#define S3C2410_UCON_UCLK	  (1<<10)

#define S3C2410_UCON_UCLK	  (1<<10)

#define S3C2410_UCON_SBREAK	  (1<<4)

#define S3C2410_UCON_SBREAK	  (1<<4)
@@ -193,6 +198,7 @@ 




/* Following are specific to S5PV210 */

/* Following are specific to S5PV210 */

#define S5PV210_UCON_CLKMASK	(1<<10)

#define S5PV210_UCON_CLKMASK	(1<<10)

#define S5PV210_UCON_CLKSHIFT	(10)

#define S5PV210_UCON_PCLK	(0<<10)

#define S5PV210_UCON_PCLK	(0<<10)

#define S5PV210_UCON_UCLK	(1<<10)

#define S5PV210_UCON_UCLK	(1<<10)
@@ -221,7 +227,6 @@ 
#define S5PV210_UFSTAT_RXMASK	(255<<0)

#define S5PV210_UFSTAT_RXMASK	(255<<0)

#define S5PV210_UFSTAT_RXSHIFT	(0)

#define S5PV210_UFSTAT_RXSHIFT	(0)





#define NO_NEED_CHECK_CLKSRC	1

#define S3C2410_UCON_CLKSEL0	(1 << 0)

#define S3C2410_UCON_CLKSEL0	(1 << 0)

#define S3C2410_UCON_CLKSEL1	(1 << 1)

#define S3C2410_UCON_CLKSEL1	(1 << 1)

#define S3C2410_UCON_CLKSEL2	(1 << 2)

#define S3C2410_UCON_CLKSEL2	(1 << 2)

drivers/tty/serial/s3c2410.c

+4 −27
Original line number Original line Diff line number Diff line
@@ -25,31 +25,6 @@ 




#include "samsung.h"

#include "samsung.h"





static int s3c2410_serial_setsource(struct uart_port *port,

				    struct s3c24xx_uart_clksrc *clk)

{

	unsigned long ucon = rd_regl(port, S3C2410_UCON);



	if (strcmp(clk->name, "uclk") == 0)

		ucon |= S3C2410_UCON_UCLK;

	else

		ucon &= ~S3C2410_UCON_UCLK;



	wr_regl(port, S3C2410_UCON, ucon);

	return 0;

}



static int s3c2410_serial_getsource(struct uart_port *port,

				    struct s3c24xx_uart_clksrc *clk)

{

	unsigned long ucon = rd_regl(port, S3C2410_UCON);



	clk->divisor = 1;

	clk->name = (ucon & S3C2410_UCON_UCLK) ? "uclk" : "pclk";



	return 0;

}



static int s3c2410_serial_resetport(struct uart_port *port,

static int s3c2410_serial_resetport(struct uart_port *port,

				    struct s3c2410_uartcfg *cfg)

				    struct s3c2410_uartcfg *cfg)

{

{
@@ -77,8 +52,10 @@ static struct s3c24xx_uart_info s3c2410_uart_inf = { 
	.tx_fifofull	= S3C2410_UFSTAT_TXFULL,

	.tx_fifofull	= S3C2410_UFSTAT_TXFULL,

	.tx_fifomask	= S3C2410_UFSTAT_TXMASK,

	.tx_fifomask	= S3C2410_UFSTAT_TXMASK,

	.tx_fifoshift	= S3C2410_UFSTAT_TXSHIFT,

	.tx_fifoshift	= S3C2410_UFSTAT_TXSHIFT,

	.get_clksrc	= s3c2410_serial_getsource,

	.def_clk_sel	= S3C2410_UCON_CLKSEL0,

	.set_clksrc	= s3c2410_serial_setsource,

	.num_clks	= 2,

	.clksel_mask	= S3C2410_UCON_CLKMASK,

	.clksel_shift	= S3C2410_UCON_CLKSHIFT,

	.reset_port	= s3c2410_serial_resetport,

	.reset_port	= s3c2410_serial_resetport,

};

};

drivers/tty/serial/s3c2412.c

+4 −51
Original line number Original line Diff line number Diff line
@@ -25,55 +25,6 @@ 




#include "samsung.h"

#include "samsung.h"





static int s3c2412_serial_setsource(struct uart_port *port,

				     struct s3c24xx_uart_clksrc *clk)

{

	unsigned long ucon = rd_regl(port, S3C2410_UCON);



	ucon &= ~S3C2412_UCON_CLKMASK;



	if (strcmp(clk->name, "uclk") == 0)

		ucon |= S3C2440_UCON_UCLK;

	else if (strcmp(clk->name, "pclk") == 0)

		ucon |= S3C2440_UCON_PCLK;

	else if (strcmp(clk->name, "usysclk") == 0)

		ucon |= S3C2412_UCON_USYSCLK;

	else {

		printk(KERN_ERR "unknown clock source %s\n", clk->name);

		return -EINVAL;

	}



	wr_regl(port, S3C2410_UCON, ucon);

	return 0;

}





static int s3c2412_serial_getsource(struct uart_port *port,

				    struct s3c24xx_uart_clksrc *clk)

{

	unsigned long ucon = rd_regl(port, S3C2410_UCON);



	switch (ucon & S3C2412_UCON_CLKMASK) {

	case S3C2412_UCON_UCLK:

		clk->divisor = 1;

		clk->name = "uclk";

		break;



	case S3C2412_UCON_PCLK:

	case S3C2412_UCON_PCLK2:

		clk->divisor = 1;

		clk->name = "pclk";

		break;



	case S3C2412_UCON_USYSCLK:

		clk->divisor = 1;

		clk->name = "usysclk";

		break;

	}



	return 0;

}



static int s3c2412_serial_resetport(struct uart_port *port,

static int s3c2412_serial_resetport(struct uart_port *port,

				    struct s3c2410_uartcfg *cfg)

				    struct s3c2410_uartcfg *cfg)

{

{
@@ -108,8 +59,10 @@ static struct s3c24xx_uart_info s3c2412_uart_inf = { 
	.tx_fifofull	= S3C2440_UFSTAT_TXFULL,

	.tx_fifofull	= S3C2440_UFSTAT_TXFULL,

	.tx_fifomask	= S3C2440_UFSTAT_TXMASK,

	.tx_fifomask	= S3C2440_UFSTAT_TXMASK,

	.tx_fifoshift	= S3C2440_UFSTAT_TXSHIFT,

	.tx_fifoshift	= S3C2440_UFSTAT_TXSHIFT,

	.get_clksrc	= s3c2412_serial_getsource,

	.def_clk_sel	= S3C2410_UCON_CLKSEL2,

	.set_clksrc	= s3c2412_serial_setsource,

	.num_clks	= 4,

	.clksel_mask	= S3C2412_UCON_CLKMASK,

	.clksel_shift	= S3C2412_UCON_CLKSHIFT,

	.reset_port	= s3c2412_serial_resetport,

	.reset_port	= s3c2412_serial_resetport,

};

};

drivers/tty/serial/s3c2440.c

+4 −54
Original line number Original line Diff line number Diff line
@@ -25,58 +25,6 @@ 




#include "samsung.h"

#include "samsung.h"







static int s3c2440_serial_setsource(struct uart_port *port,

				     struct s3c24xx_uart_clksrc *clk)

{

	unsigned long ucon = rd_regl(port, S3C2410_UCON);



	/* todo - proper fclk<>nonfclk switch. */



	ucon &= ~S3C2440_UCON_CLKMASK;



	if (strcmp(clk->name, "uclk") == 0)

		ucon |= S3C2440_UCON_UCLK;

	else if (strcmp(clk->name, "pclk") == 0)

		ucon |= S3C2440_UCON_PCLK;

	else if (strcmp(clk->name, "fclk_n") == 0)

		ucon |= S3C2440_UCON_FCLK;

	else {

		printk(KERN_ERR "unknown clock source %s\n", clk->name);

		return -EINVAL;

	}



	wr_regl(port, S3C2410_UCON, ucon);

	return 0;

}





static int s3c2440_serial_getsource(struct uart_port *port,

				    struct s3c24xx_uart_clksrc *clk)

{

	unsigned long ucon = rd_regl(port, S3C2410_UCON);



	switch (ucon & S3C2440_UCON_CLKMASK) {

	case S3C2440_UCON_UCLK:

		clk->divisor = 1;

		clk->name = "uclk";

		break;



	case S3C2440_UCON_PCLK:

	case S3C2440_UCON_PCLK2:

		clk->divisor = 1;

		clk->name = "pclk";

		break;



	case S3C2440_UCON_FCLK:

		clk->divisor = 1;

		clk->name = "fclk_n";

		break;

	}



	return 0;

}



static int s3c2440_serial_resetport(struct uart_port *port,

static int s3c2440_serial_resetport(struct uart_port *port,

				    struct s3c2410_uartcfg *cfg)

				    struct s3c2410_uartcfg *cfg)

{

{
@@ -110,8 +58,10 @@ static struct s3c24xx_uart_info s3c2440_uart_inf = { 
	.tx_fifofull	= S3C2440_UFSTAT_TXFULL,

	.tx_fifofull	= S3C2440_UFSTAT_TXFULL,

	.tx_fifomask	= S3C2440_UFSTAT_TXMASK,

	.tx_fifomask	= S3C2440_UFSTAT_TXMASK,

	.tx_fifoshift	= S3C2440_UFSTAT_TXSHIFT,

	.tx_fifoshift	= S3C2440_UFSTAT_TXSHIFT,

	.get_clksrc	= s3c2440_serial_getsource,

	.def_clk_sel	= S3C2410_UCON_CLKSEL2,

	.set_clksrc	= s3c2440_serial_setsource,

	.num_clks	= 4,

	.clksel_mask	= S3C2440_UCON_CLKMASK,

	.clksel_shift	= S3C2440_UCON_CLKSHIFT,

	.reset_port	= s3c2440_serial_resetport,

	.reset_port	= s3c2440_serial_resetport,

};

};