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Commit bb408dd2 authored by Ville Syrjälä's avatar Ville Syrjälä
Browse files

drm/i915: Use a loop for the "three times for luck" DPLL procedure 



The magic "enable the  DPLL three times" sequence feels like it
deserves a loop.

Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20170601143619.27840-4-ville.syrjala@linux.intel.com


Reviewed-by: default avatarJani Nikula <jani.nikula@intel.com>
Reviewed-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: default avatarMaarten Lankhorst <maarten.lankhorst@linux.intel.com>
parent da1d0e26

drivers/gpu/drm/i915/intel_display.c

+6 −9
Original line number Diff line number Diff line
@@ -1550,6 +1550,7 @@ static void i9xx_enable_pll(struct intel_crtc *crtc) 
	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);

	i915_reg_t reg = DPLL(crtc->pipe);

	u32 dpll = crtc->config->dpll_hw_state.dpll;

	int i;



	assert_pipe_disabled(dev_priv, crtc->pipe);
@@ -1596,15 +1597,11 @@ static void i9xx_enable_pll(struct intel_crtc *crtc) 
	}



	/* We do this three times for luck */

	for (i = 0; i < 3; i++) {

		I915_WRITE(reg, dpll);

		POSTING_READ(reg);

		udelay(150); /* wait for warmup */

	I915_WRITE(reg, dpll);

	POSTING_READ(reg);

	udelay(150); /* wait for warmup */

	I915_WRITE(reg, dpll);

	POSTING_READ(reg);

	udelay(150); /* wait for warmup */

	}

}



/**