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Commit b9562545 authored by Hauke Mehrtens's avatar Hauke Mehrtens Committed by John W. Linville
Browse files

bcma: complete workaround for BCMA43224 and BCM4313 



This code is based on the Broadcom SDK and brcmsmac.

Signed-off-by: default avatarHauke Mehrtens <hauke@hauke-m.de>
Signed-off-by: default avatarJohn W. Linville <linville@tuxdriver.com>
parent 02817be0

drivers/bcma/driver_chipcommon_pmu.c

+17 −5
Original line number Diff line number Diff line
@@ -139,7 +139,11 @@ void bcma_pmu_workarounds(struct bcma_drv_cc *cc) 


	switch (bus->chipinfo.id) {

	case BCMA_CHIP_ID_BCM4313:

		bcma_chipco_chipctl_maskset(cc, 0, ~0, 0x7);

		/* enable 12 mA drive strenth for 4313 and set chipControl

		   register bit 1 */

		bcma_chipco_chipctl_maskset(cc, 0,

					    BCMA_CCTRL_4313_12MA_LED_DRIVE,

					    BCMA_CCTRL_4313_12MA_LED_DRIVE);

		break;

	case BCMA_CHIP_ID_BCM4331:

	case BCMA_CHIP_ID_BCM43431:
@@ -147,12 +151,20 @@ void bcma_pmu_workarounds(struct bcma_drv_cc *cc) 
		bcma_chipco_bcm4331_ext_pa_lines_ctl(cc, true);

		break;

	case BCMA_CHIP_ID_BCM43224:

	case BCMA_CHIP_ID_BCM43421:

		/* enable 12 mA drive strenth for 43224 and set chipControl

		   register bit 15 */

		if (bus->chipinfo.rev == 0) {

			pr_err("Workarounds for 43224 rev 0 not fully "

				"implemented\n");

			bcma_chipco_chipctl_maskset(cc, 0, ~0, 0x00F000F0);

			bcma_cc_maskset32(cc, BCMA_CC_CHIPCTL,

					  BCMA_CCTRL_43224_GPIO_TOGGLE,

					  BCMA_CCTRL_43224_GPIO_TOGGLE);

			bcma_chipco_chipctl_maskset(cc, 0,

						    BCMA_CCTRL_43224A0_12MA_LED_DRIVE,

						    BCMA_CCTRL_43224A0_12MA_LED_DRIVE);

		} else {

			bcma_chipco_chipctl_maskset(cc, 0, ~0, 0xF0);

			bcma_chipco_chipctl_maskset(cc, 0,

						    BCMA_CCTRL_43224B0_12MA_LED_DRIVE,

						    BCMA_CCTRL_43224B0_12MA_LED_DRIVE);

		}

		break;

	case BCMA_CHIP_ID_BCM43225:

include/linux/bcma/bcma_driver_chipcommon.h

+8 −0
Original line number Diff line number Diff line
@@ -325,6 +325,14 @@ 
#define BCMA_CHIPCTL_4331_BT_SHD0_ON_GPIO4	BIT(16)	/* enable bt_shd0 at gpio4 */

#define BCMA_CHIPCTL_4331_BT_SHD1_ON_GPIO5	BIT(17)	/* enable bt_shd1 at gpio5 */



/* 43224 chip-specific ChipControl register bits */

#define BCMA_CCTRL_43224_GPIO_TOGGLE		0x8000		/* gpio[3:0] pins as btcoex or s/w gpio */

#define BCMA_CCTRL_43224A0_12MA_LED_DRIVE	0x00F000F0	/* 12 mA drive strength */

#define BCMA_CCTRL_43224B0_12MA_LED_DRIVE	0xF0		/* 12 mA drive strength for later 43224s */



/* 4313 Chip specific ChipControl register bits */

#define BCMA_CCTRL_4313_12MA_LED_DRIVE		0x00000007	/* 12 mA drive strengh for later 4313 */



/* Data for the PMU, if available.

 * Check availability with ((struct bcma_chipcommon)->capabilities & BCMA_CC_CAP_PMU)

 */