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Commit af2c6399 authored by Chuanxiao Dong's avatar Chuanxiao Dong Committed by Zhenyu Wang
Browse files

drm/i915/gvt: add gtt_invalidate API to flush the GTT TLB 



add gtt_invalidate API to handle the GTT TLB flush instead of
hiding in write_pte64 function. This can avoid overkill when using
write_pte64

Suggested-by: default avatarZhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: default avatarChuanxiao Dong <chuanxiao.dong@intel.com>
Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: default avatarZhenyu Wang <zhenyuw@linux.intel.com>
parent 9b7bd65e

drivers/gpu/drm/i915/gvt/gtt.c

+9 −6
Original line number Diff line number Diff line
@@ -244,15 +244,19 @@ static u64 read_pte64(struct drm_i915_private *dev_priv, unsigned long index) 
	return readq(addr);

}



static void gtt_invalidate(struct drm_i915_private *dev_priv)

{

	mmio_hw_access_pre(dev_priv);

	I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);

	mmio_hw_access_post(dev_priv);

}



static void write_pte64(struct drm_i915_private *dev_priv,

		unsigned long index, u64 pte)

{

	void __iomem *addr = (gen8_pte_t __iomem *)dev_priv->ggtt.gsm + index;



	writeq(pte, addr);



	I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);

	POSTING_READ(GFX_FLSH_CNTL_GEN6);

}



static inline struct intel_gvt_gtt_entry *gtt_get_entry64(void *pt,
@@ -1849,6 +1853,7 @@ static int emulate_gtt_mmio_write(struct intel_vgpu *vgpu, unsigned int off, 
	}



	ggtt_set_shadow_entry(ggtt_mm, &m, g_gtt_index);

	gtt_invalidate(gvt->dev_priv);

	ggtt_set_guest_entry(ggtt_mm, &e, g_gtt_index);

	return 0;

}
@@ -2301,8 +2306,6 @@ void intel_vgpu_reset_ggtt(struct intel_vgpu *vgpu) 
	u32 num_entries;

	struct intel_gvt_gtt_entry e;



	intel_runtime_pm_get(dev_priv);



	memset(&e, 0, sizeof(struct intel_gvt_gtt_entry));

	e.type = GTT_TYPE_GGTT_PTE;

	ops->set_pfn(&e, gvt->gtt.scratch_ggtt_mfn);
@@ -2318,7 +2321,7 @@ void intel_vgpu_reset_ggtt(struct intel_vgpu *vgpu) 
	for (offset = 0; offset < num_entries; offset++)

		ops->set_entry(NULL, &e, index + offset, false, 0, vgpu);



	intel_runtime_pm_put(dev_priv);

	gtt_invalidate(dev_priv);

}



/**