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Commit a77e1c4d authored by Paul Walmsley's avatar Paul Walmsley
Browse files

Merge branches 'am35xx_hwmod_data_fixes_a_3.6', 'am35xx_emac_mdio_devel_3.6'...

Merge branches 'am35xx_hwmod_data_fixes_a_3.6', 'am35xx_emac_mdio_devel_3.6' and 'am35xx_prcm_data_devel_3.6' into am35xx_devel_3.6
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+46 −44
Original line number Diff line number Diff line
@@ -15,27 +15,13 @@
 * General Public License for more details.
 */

#include <linux/clk.h>
#include <linux/err.h>
#include <linux/davinci_emac.h>
#include <linux/platform_device.h>
#include <plat/irqs.h>
#include <asm/system.h>
#include <plat/omap_device.h>
#include <mach/am35xx.h>

#include "control.h"

static struct mdio_platform_data am35xx_emac_mdio_pdata;

static struct resource am35xx_emac_mdio_resources[] = {
	DEFINE_RES_MEM(AM35XX_IPSS_EMAC_BASE + AM35XX_EMAC_MDIO_OFFSET, SZ_4K),
};

static struct platform_device am35xx_emac_mdio_device = {
	.name		= "davinci_mdio",
	.id		= 0,
	.num_resources	= ARRAY_SIZE(am35xx_emac_mdio_resources),
	.resource	= am35xx_emac_mdio_resources,
	.dev.platform_data = &am35xx_emac_mdio_pdata,
};
#include "am35xx-emac.h"

static void am35xx_enable_emac_int(void)
{
@@ -69,41 +55,57 @@ static struct emac_platform_data am35xx_emac_pdata = {
	.interrupt_disable	= am35xx_disable_emac_int,
};

static struct resource am35xx_emac_resources[] = {
	DEFINE_RES_MEM(AM35XX_IPSS_EMAC_BASE, 0x30000),
	DEFINE_RES_IRQ(INT_35XX_EMAC_C0_RXTHRESH_IRQ),
	DEFINE_RES_IRQ(INT_35XX_EMAC_C0_RX_PULSE_IRQ),
	DEFINE_RES_IRQ(INT_35XX_EMAC_C0_TX_PULSE_IRQ),
	DEFINE_RES_IRQ(INT_35XX_EMAC_C0_MISC_PULSE_IRQ),
};
static struct mdio_platform_data am35xx_mdio_pdata;

static struct platform_device am35xx_emac_device = {
	.name		= "davinci_emac",
	.id		= -1,
	.num_resources	= ARRAY_SIZE(am35xx_emac_resources),
	.resource	= am35xx_emac_resources,
	.dev		= {
		.platform_data	= &am35xx_emac_pdata,
	},
};
static int __init omap_davinci_emac_dev_init(struct omap_hwmod *oh,
		void *pdata, int pdata_len)
{
	struct platform_device *pdev;

	pdev = omap_device_build(oh->class->name, 0, oh, pdata, pdata_len,
				 NULL, 0, false);
	if (IS_ERR(pdev)) {
		WARN(1, "Can't build omap_device for %s:%s.\n",
		     oh->class->name, oh->name);
		return PTR_ERR(pdev);
	}

	return 0;
}

void __init am35xx_emac_init(unsigned long mdio_bus_freq, u8 rmii_en)
{
	struct omap_hwmod *oh;
	u32 v;
	int err;
	int ret;

	am35xx_emac_pdata.rmii_en = rmii_en;
	am35xx_emac_mdio_pdata.bus_freq = mdio_bus_freq;
	err = platform_device_register(&am35xx_emac_device);
	if (err) {
		pr_err("AM35x: failed registering EMAC device: %d\n", err);
	oh = omap_hwmod_lookup("davinci_mdio");
	if (!oh) {
		pr_err("Could not find davinci_mdio hwmod\n");
		return;
	}

	am35xx_mdio_pdata.bus_freq = mdio_bus_freq;

	ret = omap_davinci_emac_dev_init(oh, &am35xx_mdio_pdata,
					 sizeof(am35xx_mdio_pdata));
	if (ret) {
		pr_err("Could not build davinci_mdio hwmod device\n");
		return;
	}

	err = platform_device_register(&am35xx_emac_mdio_device);
	if (err) {
		pr_err("AM35x: failed registering EMAC MDIO device: %d\n", err);
		platform_device_unregister(&am35xx_emac_device);
	oh = omap_hwmod_lookup("davinci_emac");
	if (!oh) {
		pr_err("Could not find davinci_emac hwmod\n");
		return;
	}

	am35xx_emac_pdata.rmii_en = rmii_en;

	ret = omap_davinci_emac_dev_init(oh, &am35xx_emac_pdata,
					 sizeof(am35xx_emac_pdata));
	if (ret) {
		pr_err("Could not build davinci_emac hwmod device\n");
		return;
	}

+1 −1
Original line number Diff line number Diff line
@@ -3478,7 +3478,7 @@ static struct omap_clk omap3xxx_clks[] = {
	CLK(NULL,	"ipss_ick",	&ipss_ick,	CK_AM35XX),
	CLK(NULL,	"rmii_ck",	&rmii_ck,	CK_AM35XX),
	CLK(NULL,	"pclk_ck",	&pclk_ck,	CK_AM35XX),
	CLK("davinci_emac",	NULL,	&emac_ick,	CK_AM35XX),
	CLK("davinci_emac.0",	NULL,	&emac_ick,	CK_AM35XX),
	CLK("davinci_mdio.0",	NULL,	&emac_fck,	CK_AM35XX),
	CLK("vpfe-capture",	"master",	&vpfe_ick,	CK_AM35XX),
	CLK("vpfe-capture",	"slave",	&vpfe_fck,	CK_AM35XX),
+144 −13
Original line number Diff line number Diff line
@@ -59,6 +59,12 @@ static struct clkdm_dep gfx_sgx_3xxx_wkdeps[] = {
	{ NULL },
};

static struct clkdm_dep gfx_sgx_am35x_wkdeps[] = {
	{ .clkdm_name = "mpu_clkdm" },
	{ .clkdm_name = "wkup_clkdm" },
	{ NULL },
};

/* 3430: PM_WKDEP_PER: CORE, IVA2, MPU, WKUP */
static struct clkdm_dep per_wkdeps[] = {
	{ .clkdm_name = "core_l3_clkdm" },
@@ -69,6 +75,14 @@ static struct clkdm_dep per_wkdeps[] = {
	{ NULL },
};

static struct clkdm_dep per_am35x_wkdeps[] = {
	{ .clkdm_name = "core_l3_clkdm" },
	{ .clkdm_name = "core_l4_clkdm" },
	{ .clkdm_name = "mpu_clkdm" },
	{ .clkdm_name = "wkup_clkdm" },
	{ NULL },
};

/* 3430ES2: PM_WKDEP_USBHOST: CORE, IVA2, MPU, WKUP */
static struct clkdm_dep usbhost_wkdeps[] = {
	{ .clkdm_name = "core_l3_clkdm" },
@@ -79,6 +93,14 @@ static struct clkdm_dep usbhost_wkdeps[] = {
	{ NULL },
};

static struct clkdm_dep usbhost_am35x_wkdeps[] = {
	{ .clkdm_name = "core_l3_clkdm" },
	{ .clkdm_name = "core_l4_clkdm" },
	{ .clkdm_name = "mpu_clkdm" },
	{ .clkdm_name = "wkup_clkdm" },
	{ NULL },
};

/* 3430 PM_WKDEP_MPU: CORE, IVA2, DSS, PER */
static struct clkdm_dep mpu_3xxx_wkdeps[] = {
	{ .clkdm_name = "core_l3_clkdm" },
@@ -89,6 +111,14 @@ static struct clkdm_dep mpu_3xxx_wkdeps[] = {
	{ NULL },
};

static struct clkdm_dep mpu_am35x_wkdeps[] = {
	{ .clkdm_name = "core_l3_clkdm" },
	{ .clkdm_name = "core_l4_clkdm" },
	{ .clkdm_name = "dss_clkdm" },
	{ .clkdm_name = "per_clkdm" },
	{ NULL },
};

/* 3430 PM_WKDEP_IVA2: CORE, MPU, WKUP, DSS, PER */
static struct clkdm_dep iva2_wkdeps[] = {
	{ .clkdm_name = "core_l3_clkdm" },
@@ -116,6 +146,12 @@ static struct clkdm_dep dss_wkdeps[] = {
	{ NULL },
};

static struct clkdm_dep dss_am35x_wkdeps[] = {
	{ .clkdm_name = "mpu_clkdm" },
	{ .clkdm_name = "wkup_clkdm" },
	{ NULL },
};

/* 3430: PM_WKDEP_NEON: MPU */
static struct clkdm_dep neon_wkdeps[] = {
	{ .clkdm_name = "mpu_clkdm" },
@@ -131,6 +167,11 @@ static struct clkdm_dep dss_sleepdeps[] = {
	{ NULL },
};

static struct clkdm_dep dss_am35x_sleepdeps[] = {
	{ .clkdm_name = "mpu_clkdm" },
	{ NULL },
};

/* 3430: CM_SLEEPDEP_PER: MPU, IVA */
static struct clkdm_dep per_sleepdeps[] = {
	{ .clkdm_name = "mpu_clkdm" },
@@ -138,6 +179,11 @@ static struct clkdm_dep per_sleepdeps[] = {
	{ NULL },
};

static struct clkdm_dep per_am35x_sleepdeps[] = {
	{ .clkdm_name = "mpu_clkdm" },
	{ NULL },
};

/* 3430ES2: CM_SLEEPDEP_USBHOST: MPU, IVA */
static struct clkdm_dep usbhost_sleepdeps[] = {
	{ .clkdm_name = "mpu_clkdm" },
@@ -145,6 +191,11 @@ static struct clkdm_dep usbhost_sleepdeps[] = {
	{ NULL },
};

static struct clkdm_dep usbhost_am35x_sleepdeps[] = {
	{ .clkdm_name = "mpu_clkdm" },
	{ NULL },
};

/* 3430: CM_SLEEPDEP_CAM: MPU */
static struct clkdm_dep cam_sleepdeps[] = {
	{ .clkdm_name = "mpu_clkdm" },
@@ -175,6 +226,15 @@ static struct clockdomain mpu_3xxx_clkdm = {
	.clktrctrl_mask = OMAP3430_CLKTRCTRL_MPU_MASK,
};

static struct clockdomain mpu_am35x_clkdm = {
	.name		= "mpu_clkdm",
	.pwrdm		= { .name = "mpu_pwrdm" },
	.flags		= CLKDM_CAN_HWSUP | CLKDM_CAN_FORCE_WAKEUP,
	.dep_bit	= OMAP3430_EN_MPU_SHIFT,
	.wkdep_srcs	= mpu_am35x_wkdeps,
	.clktrctrl_mask = OMAP3430_CLKTRCTRL_MPU_MASK,
};

static struct clockdomain neon_clkdm = {
	.name		= "neon_clkdm",
	.pwrdm		= { .name = "neon_pwrdm" },
@@ -210,6 +270,15 @@ static struct clockdomain sgx_clkdm = {
	.clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_SGX_MASK,
};

static struct clockdomain sgx_am35x_clkdm = {
	.name		= "sgx_clkdm",
	.pwrdm		= { .name = "sgx_pwrdm" },
	.flags		= CLKDM_CAN_HWSUP_SWSUP,
	.wkdep_srcs	= gfx_sgx_am35x_wkdeps,
	.sleepdep_srcs	= gfx_sgx_sleepdeps,
	.clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_SGX_MASK,
};

/*
 * The die-to-die clockdomain was documented in the 34xx ES1 TRM, but
 * then that information was removed from the 34xx ES2+ TRM.  It is
@@ -261,6 +330,16 @@ static struct clockdomain dss_3xxx_clkdm = {
	.clktrctrl_mask = OMAP3430_CLKTRCTRL_DSS_MASK,
};

static struct clockdomain dss_am35x_clkdm = {
	.name		= "dss_clkdm",
	.pwrdm		= { .name = "dss_pwrdm" },
	.flags		= CLKDM_CAN_HWSUP_SWSUP,
	.dep_bit	= OMAP3430_PM_WKDEP_MPU_EN_DSS_SHIFT,
	.wkdep_srcs	= dss_am35x_wkdeps,
	.sleepdep_srcs	= dss_am35x_sleepdeps,
	.clktrctrl_mask = OMAP3430_CLKTRCTRL_DSS_MASK,
};

static struct clockdomain cam_clkdm = {
	.name		= "cam_clkdm",
	.pwrdm		= { .name = "cam_pwrdm" },
@@ -279,6 +358,15 @@ static struct clockdomain usbhost_clkdm = {
	.clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_USBHOST_MASK,
};

static struct clockdomain usbhost_am35x_clkdm = {
	.name		= "usbhost_clkdm",
	.pwrdm		= { .name = "core_pwrdm" },
	.flags		= CLKDM_CAN_HWSUP_SWSUP,
	.wkdep_srcs	= usbhost_am35x_wkdeps,
	.sleepdep_srcs	= usbhost_am35x_sleepdeps,
	.clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_USBHOST_MASK,
};

static struct clockdomain per_clkdm = {
	.name		= "per_clkdm",
	.pwrdm		= { .name = "per_pwrdm" },
@@ -289,6 +377,16 @@ static struct clockdomain per_clkdm = {
	.clktrctrl_mask = OMAP3430_CLKTRCTRL_PER_MASK,
};

static struct clockdomain per_am35x_clkdm = {
	.name		= "per_clkdm",
	.pwrdm		= { .name = "per_pwrdm" },
	.flags		= CLKDM_CAN_HWSUP_SWSUP,
	.dep_bit	= OMAP3430_EN_PER_SHIFT,
	.wkdep_srcs	= per_am35x_wkdeps,
	.sleepdep_srcs	= per_am35x_sleepdeps,
	.clktrctrl_mask = OMAP3430_CLKTRCTRL_PER_MASK,
};

/*
 * Disable hw supervised mode for emu_clkdm, because emu_pwrdm is
 * switched of even if sdti is in use
@@ -341,31 +439,44 @@ static struct clkdm_autodep clkdm_autodeps[] = {
	}
};

static struct clkdm_autodep clkdm_am35x_autodeps[] = {
	{
		.clkdm = { .name = "mpu_clkdm" },
	},
	{
		.clkdm = { .name = NULL },
	}
};

/*
 *
 */

static struct clockdomain *clockdomains_omap3430_common[] __initdata = {
static struct clockdomain *clockdomains_common[] __initdata = {
	&wkup_common_clkdm,
	&cm_common_clkdm,
	&prm_common_clkdm,
	&mpu_3xxx_clkdm,
	&neon_clkdm,
	&iva2_clkdm,
	&d2d_clkdm,
	&core_l3_3xxx_clkdm,
	&core_l4_3xxx_clkdm,
	&dss_3xxx_clkdm,
	&cam_clkdm,
	&per_clkdm,
	&emu_clkdm,
	&dpll1_clkdm,
	&dpll2_clkdm,
	&dpll3_clkdm,
	&dpll4_clkdm,
	NULL
};

static struct clockdomain *clockdomains_omap3430[] __initdata = {
	&mpu_3xxx_clkdm,
	&iva2_clkdm,
	&d2d_clkdm,
	&dss_3xxx_clkdm,
	&cam_clkdm,
	&per_clkdm,
	&dpll2_clkdm,
	NULL
};

static struct clockdomain *clockdomains_omap3430es1[] __initdata = {
	&gfx_3430es1_clkdm,
	NULL,
@@ -378,21 +489,41 @@ static struct clockdomain *clockdomains_omap3430es2plus[] __initdata = {
	NULL,
};

static struct clockdomain *clockdomains_am35x[] __initdata = {
	&mpu_am35x_clkdm,
	&sgx_am35x_clkdm,
	&dss_am35x_clkdm,
	&per_am35x_clkdm,
	&usbhost_am35x_clkdm,
	&dpll5_clkdm,
	NULL
};

void __init omap3xxx_clockdomains_init(void)
{
	struct clockdomain **sc;
	unsigned int rev;

	if (!cpu_is_omap34xx())
		return;

	clkdm_register_platform_funcs(&omap3_clkdm_operations);
	clkdm_register_clkdms(clockdomains_omap3430_common);
	clkdm_register_clkdms(clockdomains_common);

	sc = (omap_rev() == OMAP3430_REV_ES1_0) ? clockdomains_omap3430es1 :
		clockdomains_omap3430es2plus;
	rev = omap_rev();

	clkdm_register_clkdms(sc);
	if (rev == AM35XX_REV_ES1_0 || rev == AM35XX_REV_ES1_1) {
		clkdm_register_clkdms(clockdomains_am35x);
		clkdm_register_autodeps(clkdm_am35x_autodeps);
	} else {
		clkdm_register_clkdms(clockdomains_omap3430);

		sc = (rev == OMAP3430_REV_ES1_0) ?
			clockdomains_omap3430es1 : clockdomains_omap3430es2plus;

		clkdm_register_clkdms(sc);
		clkdm_register_autodeps(clkdm_autodeps);
	}

	clkdm_complete_init();
}
+2 −0
Original line number Diff line number Diff line
@@ -36,6 +36,8 @@
#define AM35XX_EMAC_CNTRL_MOD_OFFSET	(0x0)
#define AM35XX_EMAC_CNTRL_RAM_OFFSET	(0x20000)
#define AM35XX_EMAC_MDIO_OFFSET		(0x30000)
#define AM35XX_IPSS_MDIO_BASE		(AM35XX_IPSS_EMAC_BASE + \
						AM35XX_EMAC_MDIO_OFFSET)
#define AM35XX_EMAC_CNTRL_RAM_SIZE	(0x2000)
#define AM35XX_EMAC_RAM_ADDR		(AM3517_EMAC_BASE + \
						AM3517_EMAC_CNTRL_RAM_OFFSET)
+105 −0
Original line number Diff line number Diff line
@@ -3154,6 +3154,107 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__counter_32k = {
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* am35xx has Davinci MDIO & EMAC */
static struct omap_hwmod_class am35xx_mdio_class = {
	.name = "davinci_mdio",
};

static struct omap_hwmod am35xx_mdio_hwmod = {
	.name		= "davinci_mdio",
	.class		= &am35xx_mdio_class,
	.flags		= HWMOD_NO_IDLEST,
};

/*
 * XXX Should be connected to an IPSS hwmod, not the L3 directly;
 * but this will probably require some additional hwmod core support,
 * so is left as a future to-do item.
 */
static struct omap_hwmod_ocp_if am35xx_mdio__l3 = {
	.master		= &am35xx_mdio_hwmod,
	.slave		= &omap3xxx_l3_main_hwmod,
	.clk		= "emac_fck",
	.user		= OCP_USER_MPU,
};

static struct omap_hwmod_addr_space am35xx_mdio_addrs[] = {
	{
		.pa_start	= AM35XX_IPSS_MDIO_BASE,
		.pa_end		= AM35XX_IPSS_MDIO_BASE + SZ_4K - 1,
		.flags		= ADDR_TYPE_RT,
	},
	{ }
};

/* l4_core -> davinci mdio  */
/*
 * XXX Should be connected to an IPSS hwmod, not the L4_CORE directly;
 * but this will probably require some additional hwmod core support,
 * so is left as a future to-do item.
 */
static struct omap_hwmod_ocp_if am35xx_l4_core__mdio = {
	.master		= &omap3xxx_l4_core_hwmod,
	.slave		= &am35xx_mdio_hwmod,
	.clk		= "emac_fck",
	.addr		= am35xx_mdio_addrs,
	.user		= OCP_USER_MPU,
};

static struct omap_hwmod_irq_info am35xx_emac_mpu_irqs[] = {
	{ .name = "rxthresh",	.irq = INT_35XX_EMAC_C0_RXTHRESH_IRQ },
	{ .name = "rx_pulse",	.irq = INT_35XX_EMAC_C0_RX_PULSE_IRQ },
	{ .name = "tx_pulse",	.irq = INT_35XX_EMAC_C0_TX_PULSE_IRQ },
	{ .name = "misc_pulse",	.irq = INT_35XX_EMAC_C0_MISC_PULSE_IRQ },
	{ .irq = -1 }
};

static struct omap_hwmod_class am35xx_emac_class = {
	.name = "davinci_emac",
};

static struct omap_hwmod am35xx_emac_hwmod = {
	.name		= "davinci_emac",
	.mpu_irqs	= am35xx_emac_mpu_irqs,
	.class		= &am35xx_emac_class,
	.flags		= HWMOD_NO_IDLEST,
};

/* l3_core -> davinci emac interface */
/*
 * XXX Should be connected to an IPSS hwmod, not the L3 directly;
 * but this will probably require some additional hwmod core support,
 * so is left as a future to-do item.
 */
static struct omap_hwmod_ocp_if am35xx_emac__l3 = {
	.master		= &am35xx_emac_hwmod,
	.slave		= &omap3xxx_l3_main_hwmod,
	.clk		= "emac_ick",
	.user		= OCP_USER_MPU,
};

static struct omap_hwmod_addr_space am35xx_emac_addrs[] = {
	{
		.pa_start	= AM35XX_IPSS_EMAC_BASE,
		.pa_end		= AM35XX_IPSS_EMAC_BASE + 0x30000 - 1,
		.flags		= ADDR_TYPE_RT,
	},
	{ }
};

/* l4_core -> davinci emac  */
/*
 * XXX Should be connected to an IPSS hwmod, not the L4_CORE directly;
 * but this will probably require some additional hwmod core support,
 * so is left as a future to-do item.
 */
static struct omap_hwmod_ocp_if am35xx_l4_core__emac = {
	.master		= &omap3xxx_l4_core_hwmod,
	.slave		= &am35xx_emac_hwmod,
	.clk		= "emac_ick",
	.addr		= am35xx_emac_addrs,
	.user		= OCP_USER_MPU,
};

static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = {
	&omap3xxx_l3_main__l4_core,
	&omap3xxx_l3_main__l4_per,
@@ -3282,6 +3383,10 @@ static struct omap_hwmod_ocp_if *am35xx_hwmod_ocp_ifs[] __initdata = {
	&omap3xxx_l4_core__usb_tll_hs,
	&omap3xxx_l4_core__es3plus_mmc1,
	&omap3xxx_l4_core__es3plus_mmc2,
	&am35xx_mdio__l3,
	&am35xx_l4_core__mdio,
	&am35xx_emac__l3,
	&am35xx_l4_core__emac,
	NULL
};

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