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Commit a3a0f8c8 authored by David VomLehn's avatar David VomLehn Committed by Ralf Baechle
Browse files

MIPS: PowerTV: Base files for Cisco PowerTV platform 



Add the Cisco Powertv cable settop box to the MIPS tree. This platform is
based on a MIPS 24Kc processor with various devices integrated on the same
ASIC. There are multiple models of this box, with differing configuration
but the same kernel runs across the product line.

Signed-off-by: default avatarDavid VomLehn <dvomlehn@cisco.com>
Cc: linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/132/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 13e79b46

arch/mips/Kconfig

+22 −0
Original line number Original line Diff line number Diff line
@@ -338,6 +338,24 @@ config PMC_YOSEMITE 
	  Yosemite is an evaluation board for the RM9000x2 processor

	  Yosemite is an evaluation board for the RM9000x2 processor

	  manufactured by PMC-Sierra.

	  manufactured by PMC-Sierra.





config POWERTV

	bool "Cisco PowerTV"

	select BOOT_ELF32

	select CEVT_R4K

	select CPU_MIPSR2_IRQ_VI

	select CPU_MIPSR2_IRQ_EI

	select CSRC_POWERTV

	select DMA_NONCOHERENT

	select HW_HAS_PCI

	select SYS_HAS_EARLY_PRINTK

	select SYS_HAS_CPU_MIPS32_R2

	select SYS_SUPPORTS_32BIT_KERNEL

	select SYS_SUPPORTS_BIG_ENDIAN

	select SYS_SUPPORTS_HIGHMEM

	select USB_OHCI_LITTLE_ENDIAN

	help

	  This enables support for the Cisco PowerTV Platform.



config SGI_IP22

config SGI_IP22

	bool "SGI IP22 (Indy/Indigo2)"

	bool "SGI IP22 (Indy/Indigo2)"

	select ARC

	select ARC
@@ -683,6 +701,7 @@ source "arch/mips/bcm63xx/Kconfig" 
source "arch/mips/jazz/Kconfig"

source "arch/mips/jazz/Kconfig"

source "arch/mips/lasat/Kconfig"

source "arch/mips/lasat/Kconfig"

source "arch/mips/pmc-sierra/Kconfig"

source "arch/mips/pmc-sierra/Kconfig"

source "arch/mips/powertv/Kconfig"

source "arch/mips/sgi-ip27/Kconfig"

source "arch/mips/sgi-ip27/Kconfig"

source "arch/mips/sibyte/Kconfig"

source "arch/mips/sibyte/Kconfig"

source "arch/mips/txx9/Kconfig"

source "arch/mips/txx9/Kconfig"
@@ -782,6 +801,9 @@ config CSRC_BCM1480 
config CSRC_IOASIC

config CSRC_IOASIC

	bool

	bool





config CSRC_POWERTV

	bool



config CSRC_R4K_LIB

config CSRC_R4K_LIB

	bool

	bool

arch/mips/Makefile

+7 −0
Original line number Original line Diff line number Diff line
@@ -444,6 +444,13 @@ cflags-$(CONFIG_SOC_EMMA2RH) += -I$(srctree)/arch/mips/include/asm/mach-emma2rh 
core-$(CONFIG_NEC_MARKEINS)	+= arch/mips/emma/markeins/

core-$(CONFIG_NEC_MARKEINS)	+= arch/mips/emma/markeins/

load-$(CONFIG_NEC_MARKEINS)	+= 0xffffffff88100000

load-$(CONFIG_NEC_MARKEINS)	+= 0xffffffff88100000





#

# Cisco PowerTV Platform

#

core-$(CONFIG_POWERTV)		+= arch/mips/powertv/

cflags-$(CONFIG_POWERTV)        += -I$(srctree)/arch/mips/include/asm/mach-powertv

load-$(CONFIG_POWERTV)		+= 0xffffffff90800000



#

#

# SGI IP22 (Indy/Indigo2)

# SGI IP22 (Indy/Indigo2)

#

#

arch/mips/configs/powertv_defconfig

0 → 100644
+1549 −0

File added.

Preview size limit exceeded, changes collapsed.

arch/mips/include/asm/mach-powertv/asic.h

0 → 100644
+107 −0
Original line number Original line Diff line number Diff line 
/*

 * Copyright (C) 2009  Cisco Systems, Inc.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License as published by

 * the Free Software Foundation; either version 2 of the License, or

 * (at your option) any later version.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 *

 * You should have received a copy of the GNU General Public License

 * along with this program; if not, write to the Free Software

 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA

 */



#ifndef _ASM_MACH_POWERTV_ASIC_H

#define _ASM_MACH_POWERTV_ASIC_H



#include <linux/ioport.h>

#include <asm/mach-powertv/asic_regs.h>



#define DVR_CAPABLE     (1<<0)

#define PCIE_CAPABLE    (1<<1)

#define FFS_CAPABLE     (1<<2)

#define DISPLAY_CAPABLE (1<<3)



/* Platform Family types

 * For compitability, the new value must be added in the end */

enum family_type {

	FAMILY_8500,

	FAMILY_8500RNG,

	FAMILY_4500,

	FAMILY_1500,

	FAMILY_8600,

	FAMILY_4600,

	FAMILY_4600VZA,

	FAMILY_8600VZB,

	FAMILY_1500VZE,

	FAMILY_1500VZF,

	FAMILIES

};



/* Register maps for each ASIC */

extern const struct register_map calliope_register_map;

extern const struct register_map cronus_register_map;

extern const struct register_map zeus_register_map;



extern struct resource dvr_cronus_resources[];

extern struct resource dvr_zeus_resources[];

extern struct resource non_dvr_calliope_resources[];

extern struct resource non_dvr_cronus_resources[];

extern struct resource non_dvr_cronuslite_resources[];

extern struct resource non_dvr_vz_calliope_resources[];

extern struct resource non_dvr_vze_calliope_resources[];

extern struct resource non_dvr_vzf_calliope_resources[];

extern struct resource non_dvr_zeus_resources[];



extern void powertv_platform_init(void);

extern void platform_alloc_bootmem(void);

extern enum asic_type platform_get_asic(void);

extern enum family_type platform_get_family(void);

extern int platform_supports_dvr(void);

extern int platform_supports_ffs(void);

extern int platform_supports_pcie(void);

extern int platform_supports_display(void);

extern void configure_platform(void);

extern void platform_configure_usb_ehci(void);

extern void platform_unconfigure_usb_ehci(void);

extern void platform_configure_usb_ohci(void);

extern void platform_unconfigure_usb_ohci(void);



/* Platform Resources */

#define ASIC_RESOURCE_GET_EXISTS 1

extern struct resource *asic_resource_get(const char *name);

extern void platform_release_memory(void *baddr, int size);



/* Reboot Cause */

extern void set_reboot_cause(char code, unsigned int data, unsigned int data2);

extern void set_locked_reboot_cause(char code, unsigned int data,

	unsigned int data2);



enum sys_reboot_type {

	sys_unknown_reboot = 0x00,	/* Unknown reboot cause */

	sys_davic_change = 0x01,	/* Reboot due to change in DAVIC

					 * mode */

	sys_user_reboot = 0x02,		/* Reboot initiated by user */

	sys_system_reboot = 0x03,	/* Reboot initiated by OS */

	sys_trap_reboot = 0x04,		/* Reboot due to a CPU trap */

	sys_silent_reboot = 0x05,	/* Silent reboot */

	sys_boot_ldr_reboot = 0x06,	/* Bootloader reboot */

	sys_power_up_reboot = 0x07,	/* Power on bootup.  Older

					 * drivers may report as

					 * userReboot. */

	sys_code_change = 0x08,		/* Reboot to take code change.

					 * Older drivers may report as

					 * userReboot. */

	sys_hardware_reset = 0x09,	/* HW watchdog or front-panel

					 * reset button reset.  Older

					 * drivers may report as

					 * userReboot. */

	sys_watchdogInterrupt = 0x0A	/* Pre-watchdog interrupt */

};



#endif /* _ASM_MACH_POWERTV_ASIC_H */

arch/mips/include/asm/mach-powertv/asic_regs.h

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+155 −0
Original line number Original line Diff line number Diff line 
/*

 * Copyright (C) 2009  Cisco Systems, Inc.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License as published by

 * the Free Software Foundation; either version 2 of the License, or

 * (at your option) any later version.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 *

 * You should have received a copy of the GNU General Public License

 * along with this program; if not, write to the Free Software

 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA

 */



#ifndef __ASM_MACH_POWERTV_ASIC_H_

#define __ASM_MACH_POWERTV_ASIC_H_

#include <linux/io.h>



/* ASIC types */

enum asic_type {

	ASIC_UNKNOWN,

	ASIC_ZEUS,

	ASIC_CALLIOPE,

	ASIC_CRONUS,

	ASIC_CRONUSLITE,

	ASICS

};



/* hardcoded values read from Chip Version registers */

#define CRONUS_10	0x0B4C1C20

#define CRONUS_11	0x0B4C1C21

#define CRONUSLITE_10	0x0B4C1C40



#define NAND_FLASH_BASE	0x03000000

#define ZEUS_IO_BASE	0x09000000

#define CALLIOPE_IO_BASE	0x08000000

#define CRONUS_IO_BASE	0x09000000

#define ASIC_IO_SIZE	0x01000000



/* Definitions for backward compatibility */

#define UART1_INTSTAT	uart1_intstat

#define UART1_INTEN	uart1_inten

#define UART1_CONFIG1	uart1_config1

#define UART1_CONFIG2	uart1_config2

#define UART1_DIVISORHI	uart1_divisorhi

#define UART1_DIVISORLO	uart1_divisorlo

#define UART1_DATA	uart1_data

#define UART1_STATUS	uart1_status



/* ASIC register enumeration */

struct register_map {

	u32 eic_slow0_strt_add;

	u32 eic_cfg_bits;

	u32 eic_ready_status;



	u32 chipver3;

	u32 chipver2;

	u32 chipver1;

	u32 chipver0;



	u32 uart1_intstat;

	u32 uart1_inten;

	u32 uart1_config1;

	u32 uart1_config2;

	u32 uart1_divisorhi;

	u32 uart1_divisorlo;

	u32 uart1_data;

	u32 uart1_status;



	u32 int_stat_3;

	u32 int_stat_2;

	u32 int_stat_1;

	u32 int_stat_0;

	u32 int_config;

	u32 int_int_scan;

	u32 ien_int_3;

	u32 ien_int_2;

	u32 ien_int_1;

	u32 ien_int_0;

	u32 int_level_3_3;

	u32 int_level_3_2;

	u32 int_level_3_1;

	u32 int_level_3_0;

	u32 int_level_2_3;

	u32 int_level_2_2;

	u32 int_level_2_1;

	u32 int_level_2_0;

	u32 int_level_1_3;

	u32 int_level_1_2;

	u32 int_level_1_1;

	u32 int_level_1_0;

	u32 int_level_0_3;

	u32 int_level_0_2;

	u32 int_level_0_1;

	u32 int_level_0_0;

	u32 int_docsis_en;



	u32 mips_pll_setup;

	u32 usb_fs;

	u32 test_bus;

	u32 crt_spare;

	u32 usb2_ohci_int_mask;

	u32 usb2_strap;

	u32 ehci_hcapbase;

	u32 ohci_hc_revision;

	u32 bcm1_bs_lmi_steer;

	u32 usb2_control;

	u32 usb2_stbus_obc;

	u32 usb2_stbus_mess_size;

	u32 usb2_stbus_chunk_size;



	u32 pcie_regs;

	u32 tim_ch;

	u32 tim_cl;

	u32 gpio_dout;

	u32 gpio_din;

	u32 gpio_dir;

	u32 watchdog;

	u32 front_panel;



	u32 register_maps;

};



extern enum asic_type asic;

extern const struct register_map *register_map;

extern unsigned long asic_phy_base;	/* Physical address of ASIC */

extern unsigned long asic_base;		/* Virtual address of ASIC */



/*

 * Macros to interface to registers through their ioremapped address

 * asic_reg_offset	Returns the offset of a given register from the start

 *			of the ASIC address space

 * asic_reg_phys_addr	Returns the physical address of the given register

 * asic_reg_addr	Returns the iomapped virtual address of the given

 *			register.

 */

#define asic_reg_offset(x)	(register_map->x)

#define asic_reg_phys_addr(x)	(asic_phy_base + asic_reg_offset(x))

#define asic_reg_addr(x) \

	((unsigned int *) (asic_base + asic_reg_offset(x)))



/*

 * The asic_reg macro is gone. It should be replaced by either asic_read or

 * asic_write, as appropriate.

 */



#define asic_read(x)		readl(asic_reg_addr(x))

#define asic_write(v, x)	writel(v, asic_reg_addr(x))



extern void asic_irq_init(void);

#endif