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Commit a1dcba90 authored by fred gao's avatar fred gao Committed by Zhenyu Wang
Browse files

drm/i915/gvt: Legacy HSW related MMIO handler clean up 



remove all the legacy pre-BDW mmio handlers and the corresponding
usage/definition since pre-BDW platforms are not supported in GVT
environment.

v2:
- clean up all the left dirty code before BDW, e.g
  all D_HSW usage and itself, D_IVB, D_PRE_BDW. (Zhenyu)
v3:
- change is based on gvt-staging. (Zhenyu)

Signed-off-by: default avatarfred gao <fred.gao@intel.com>
Signed-off-by: default avatarZhenyu Wang <zhenyuw@linux.intel.com>
parent f100daec

drivers/gpu/drm/i915/gvt/handlers.c

+10 −12
Original line number Diff line number Diff line
@@ -1605,7 +1605,7 @@ static int init_generic_mmio_info(struct intel_gvt *gvt) 
	MMIO_RING_DFH(RING_REG, D_ALL, 0, instdone_mmio_read, NULL);

	MMIO_DH(RING_REG(GEN8_BSD2_RING_BASE), D_ALL, instdone_mmio_read, NULL);

#undef RING_REG

	MMIO_DH(GEN7_SC_INSTDONE, D_HSW_PLUS, instdone_mmio_read, NULL);

	MMIO_DH(GEN7_SC_INSTDONE, D_BDW_PLUS, instdone_mmio_read, NULL);



	MMIO_GM_RDR(0x2148, D_ALL, NULL, NULL);

	MMIO_GM_RDR(CCID, D_ALL, NULL, NULL);
@@ -2190,7 +2190,7 @@ static int init_generic_mmio_info(struct intel_gvt *gvt) 
	MMIO_DFH(GTFIFODBG, D_ALL, F_CMD_ACCESS, NULL, NULL);

	MMIO_DFH(GTFIFOCTL, D_ALL, F_CMD_ACCESS, NULL, NULL);

	MMIO_DH(FORCEWAKE_MT, D_PRE_SKL, NULL, mul_force_wake_write);

	MMIO_DH(FORCEWAKE_ACK_HSW, D_HSW | D_BDW, NULL, NULL);

	MMIO_DH(FORCEWAKE_ACK_HSW, D_BDW, NULL, NULL);

	MMIO_D(ECOBUS, D_ALL);

	MMIO_DH(GEN6_RC_CONTROL, D_ALL, NULL, NULL);

	MMIO_DH(GEN6_RC_STATE, D_ALL, NULL, NULL);
@@ -2222,12 +2222,12 @@ static int init_generic_mmio_info(struct intel_gvt *gvt) 
	MMIO_D(GEN6_RC6p_THRESHOLD, D_ALL);

	MMIO_D(GEN6_RC6pp_THRESHOLD, D_ALL);

	MMIO_D(GEN6_PMINTRMSK, D_ALL);

	MMIO_DH(HSW_PWR_WELL_BIOS, D_HSW | D_BDW, NULL, power_well_ctl_mmio_write);

	MMIO_DH(HSW_PWR_WELL_DRIVER, D_HSW | D_BDW, NULL, power_well_ctl_mmio_write);

	MMIO_DH(HSW_PWR_WELL_KVMR, D_HSW | D_BDW, NULL, power_well_ctl_mmio_write);

	MMIO_DH(HSW_PWR_WELL_DEBUG, D_HSW | D_BDW, NULL, power_well_ctl_mmio_write);

	MMIO_DH(HSW_PWR_WELL_CTL5, D_HSW | D_BDW, NULL, power_well_ctl_mmio_write);

	MMIO_DH(HSW_PWR_WELL_CTL6, D_HSW | D_BDW, NULL, power_well_ctl_mmio_write);

	MMIO_DH(HSW_PWR_WELL_BIOS, D_BDW, NULL, power_well_ctl_mmio_write);

	MMIO_DH(HSW_PWR_WELL_DRIVER, D_BDW, NULL, power_well_ctl_mmio_write);

	MMIO_DH(HSW_PWR_WELL_KVMR, D_BDW, NULL, power_well_ctl_mmio_write);

	MMIO_DH(HSW_PWR_WELL_DEBUG, D_BDW, NULL, power_well_ctl_mmio_write);

	MMIO_DH(HSW_PWR_WELL_CTL5, D_BDW, NULL, power_well_ctl_mmio_write);

	MMIO_DH(HSW_PWR_WELL_CTL6, D_BDW, NULL, power_well_ctl_mmio_write);



	MMIO_D(RSTDBYCTL, D_ALL);
@@ -2245,7 +2245,6 @@ static int init_generic_mmio_info(struct intel_gvt *gvt) 


	MMIO_F(0x4f000, 0x90, 0, 0, 0, D_ALL, NULL, NULL);



	MMIO_D(GEN6_PCODE_MAILBOX, D_PRE_BDW);

	MMIO_D(GEN6_PCODE_DATA, D_ALL);

	MMIO_D(0x13812c, D_ALL);

	MMIO_DH(GEN7_ERR_INT, D_ALL, NULL, NULL);
@@ -2324,14 +2323,13 @@ static int init_generic_mmio_info(struct intel_gvt *gvt) 
	MMIO_D(0x1a054, D_ALL);



	MMIO_D(0x44070, D_ALL);

	MMIO_DFH(0x215c, D_HSW_PLUS, F_CMD_ACCESS, NULL, NULL);

	MMIO_DFH(0x215c, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);

	MMIO_DFH(0x2178, D_ALL, F_CMD_ACCESS, NULL, NULL);

	MMIO_DFH(0x217c, D_ALL, F_CMD_ACCESS, NULL, NULL);

	MMIO_DFH(0x12178, D_ALL, F_CMD_ACCESS, NULL, NULL);

	MMIO_DFH(0x1217c, D_ALL, F_CMD_ACCESS, NULL, NULL);



	MMIO_F(0x2290, 8, F_CMD_ACCESS, 0, 0, D_HSW_PLUS, NULL, NULL);

	MMIO_DFH(GEN7_OACONTROL, D_HSW, F_CMD_ACCESS, NULL, NULL);

	MMIO_F(0x2290, 8, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, NULL, NULL);

	MMIO_D(0x2b00, D_BDW_PLUS);

	MMIO_D(0x2360, D_BDW_PLUS);

	MMIO_F(0x5200, 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);

drivers/gpu/drm/i915/gvt/mmio.h

+5 −13
Original line number Diff line number Diff line
@@ -39,26 +39,18 @@ 
struct intel_gvt;

struct intel_vgpu;



#define D_SNB   (1 << 0)

#define D_IVB   (1 << 1)

#define D_HSW   (1 << 2)

#define D_BDW   (1 << 3)

#define D_SKL	(1 << 4)

#define D_KBL	(1 << 5)

#define D_BDW   (1 << 0)

#define D_SKL	(1 << 1)

#define D_KBL	(1 << 2)



#define D_GEN9PLUS	(D_SKL | D_KBL)

#define D_GEN8PLUS	(D_BDW | D_SKL | D_KBL)

#define D_GEN75PLUS	(D_HSW | D_BDW | D_SKL | D_KBL)

#define D_GEN7PLUS	(D_IVB | D_HSW | D_BDW | D_SKL | D_KBL)



#define D_SKL_PLUS	(D_SKL | D_KBL)

#define D_BDW_PLUS	(D_BDW | D_SKL | D_KBL)

#define D_HSW_PLUS	(D_HSW | D_BDW | D_SKL | D_KBL)

#define D_IVB_PLUS	(D_IVB | D_HSW | D_BDW | D_SKL | D_KBL)



#define D_PRE_BDW	(D_SNB | D_IVB | D_HSW)

#define D_PRE_SKL	(D_SNB | D_IVB | D_HSW | D_BDW)

#define D_ALL		(D_SNB | D_IVB | D_HSW | D_BDW | D_SKL | D_KBL)

#define D_PRE_SKL	(D_BDW)

#define D_ALL		(D_BDW | D_SKL | D_KBL)



struct intel_gvt_mmio_info {

	u32 offset;