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Commit 9dffe3be authored by Venu Byravarasu's avatar Venu Byravarasu Committed by Stephen Warren
Browse files

ARM: tegra: modify ULPI reset GPIO properties 



1. All Tegra20 ULPI reset GPIO DT properties are modified to indicate active
low nature of the GPIO.
2. Placed USB PHY DT node immediately below the EHCI controller DT nodes
and corrected reg value in the name of USB PHY DT node.

Signed-off-by: default avatarVenu Byravarasu <vbyravarasu@nvidia.com>
Signed-off-by: default avatarStephen Warren <swarren@nvidia.com>
parent d400f209

arch/arm/boot/dts/tegra20-colibri-512.dtsi

+5 −1
Original line number Diff line number Diff line
@@ -449,7 +449,11 @@ 


	usb@c5004000 {

		status = "okay";

		nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */

		nvidia,phy-reset-gpio = <&gpio 169 1>; /* gpio PV1, active low */

	};



	usb-phy@c5004000 {

		nvidia,phy-reset-gpio = <&gpio 169 1>; /* gpio PV1, active low */

	};



	sdhci@c8000600 {

arch/arm/boot/dts/tegra20-harmony.dts

+5 −5
Original line number Diff line number Diff line
@@ -430,15 +430,15 @@ 


	usb@c5004000 {

		status = "okay";

		nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */

		nvidia,phy-reset-gpio = <&gpio 169 1>; /* gpio PV1, active low */

	};



	usb@c5008000 {

		status = "okay";

	usb-phy@c5004000 {

		nvidia,phy-reset-gpio = <&gpio 169 1>; /* gpio PV1, active low */

	};



	usb-phy@c5004400 {

		nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */

	usb@c5008000 {

		status = "okay";

	};



	sdhci@c8000200 {

arch/arm/boot/dts/tegra20-paz00.dts

+5 −5
Original line number Diff line number Diff line
@@ -429,15 +429,15 @@ 


	usb@c5004000 {

		status = "okay";

		nvidia,phy-reset-gpio = <&gpio 168 0>; /* gpio PV0 */

		nvidia,phy-reset-gpio = <&gpio 168 1>; /* gpio PV0, active low */

	};



	usb@c5008000 {

		status = "okay";

	usb-phy@c5004000 {

		nvidia,phy-reset-gpio = <&gpio 168 1>; /* gpio PV0, active low */

	};



	usb-phy@c5004400 {

		nvidia,phy-reset-gpio = <&gpio 168 0>; /* gpio PV0 */

	usb@c5008000 {

		status = "okay";

	};



	sdhci@c8000000 {

arch/arm/boot/dts/tegra20-seaboard.dts

+5 −5
Original line number Diff line number Diff line
@@ -571,15 +571,15 @@ 


	usb@c5004000 {

		status = "okay";

		nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */

		nvidia,phy-reset-gpio = <&gpio 169 1>; /* gpio PV1, active low */

	};



	usb@c5008000 {

		status = "okay";

	usb-phy@c5004000 {

		nvidia,phy-reset-gpio = <&gpio 169 1>; /* gpio PV1, active low */

	};



	usb-phy@c5004400 {

		nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */

	usb@c5008000 {

		status = "okay";

	};



	sdhci@c8000000 {

arch/arm/boot/dts/tegra20-trimslice.dts

+5 −5
Original line number Diff line number Diff line
@@ -316,15 +316,15 @@ 


	usb@c5004000 {

		status = "okay";

		nvidia,phy-reset-gpio = <&gpio 168 0>; /* gpio PV0 */

		nvidia,phy-reset-gpio = <&gpio 168 1>; /* gpio PV0, active low */

	};



	usb@c5008000 {

		status = "okay";

	usb-phy@c5004000 {

		nvidia,phy-reset-gpio = <&gpio 168 1>; /* gpio PV0, active low */

	};



	usb-phy@c5004400 {

		nvidia,phy-reset-gpio = <&gpio 168 0>; /* gpio PV0 */

	usb@c5008000 {

		status = "okay";

	};



	sdhci@c8000000 {