Loading drivers/spi/spi-sun4i.c +3 −3 Original line number Diff line number Diff line Loading @@ -140,6 +140,9 @@ static void sun4i_spi_set_cs(struct spi_device *spi, bool enable) reg &= ~SUN4I_CTL_CS_MASK; reg |= SUN4I_CTL_CS(spi->chip_select); /* We want to control the chip select manually */ reg |= SUN4I_CTL_CS_MANUAL; if (enable) reg |= SUN4I_CTL_CS_LEVEL; else Loading Loading @@ -222,9 +225,6 @@ static int sun4i_spi_transfer_one(struct spi_master *master, else reg |= SUN4I_CTL_DHB; /* We want to control the chip select manually */ reg |= SUN4I_CTL_CS_MANUAL; sun4i_spi_write(sspi, SUN4I_CTL_REG, reg); /* Ensure that we have a parent clock fast enough */ Loading Loading
drivers/spi/spi-sun4i.c +3 −3 Original line number Diff line number Diff line Loading @@ -140,6 +140,9 @@ static void sun4i_spi_set_cs(struct spi_device *spi, bool enable) reg &= ~SUN4I_CTL_CS_MASK; reg |= SUN4I_CTL_CS(spi->chip_select); /* We want to control the chip select manually */ reg |= SUN4I_CTL_CS_MANUAL; if (enable) reg |= SUN4I_CTL_CS_LEVEL; else Loading Loading @@ -222,9 +225,6 @@ static int sun4i_spi_transfer_one(struct spi_master *master, else reg |= SUN4I_CTL_DHB; /* We want to control the chip select manually */ reg |= SUN4I_CTL_CS_MANUAL; sun4i_spi_write(sspi, SUN4I_CTL_REG, reg); /* Ensure that we have a parent clock fast enough */ Loading